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Patent # Description
US-9,496,289 Thin film transistor array panel and manufacturing method thereof
A thin film transistor array panel includes: a substrate; a gate line and a common voltage line electrically separated from each other and elongated parallel...
US-9,496,288 Array substrate, display panel and display apparatus
An array substrate, a display panel and a display apparatus are provided. The array substrate includes a display region and a non-display region. The...
US-9,496,287 Semiconductor device and production method therefor
This semiconductor device (100A) includes: a transparent conductive layer (3); an insulating layer (5) which is formed to cover the transparent conductive layer...
US-9,496,286 Display substrate with a common electrode and liquid crystal display panel having the same
A display substrate includes a display area corresponding to a plurality of pixels, a peripheral area surrounding the display area, a thin film transistor for...
US-9,496,285 Semiconductor device and driving method thereof
The semiconductor device includes a transistor, first to N-th switches (N is a natural number of three or more), and first to (N-1)-th capacitors. A first...
US-9,496,284 Display panel and display apparatus including the same
This disclosure provides a display panel and a display apparatus using the display panel. The display panel includes: a substrate; a first electrode formed on...
US-9,496,283 Transistor with self-aligned source and drain contacts and method of making same
A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the...
US-9,496,282 Structure and method to reduce crystal defects in epitaxial fin merge using nitride deposition
FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over a recessed buried insulator,...
US-9,496,281 Dual isolation on SSOI wafer
A method of forming fins in a dual isolation complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET)...
US-9,496,280 Semiconductor structure having logic region and analog region
A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing...
US-9,496,279 Composite substrate
Provided is a composite substrate having a semiconductor layer wherein diffusion of a metal is suppressed. This composite substrate has: a single crystal...
US-9,496,278 Nonvolatile semiconductor storage device
A nonvolatile semiconductor storage device includes a plurality of electrode films stacked in a first direction; a silicon pillar piercing the stacked electrode...
US-9,496,277 Vertical-type semiconductor devices and methods of manufacturing the same
In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern...
US-9,496,276 CMP fabrication solution for split gate memory embedded in HK-MG process
A semiconductor device includes a substrate, at least one logic device and a split gate memory device. The at least one logic device is located on the...
US-9,496,275 Semiconductor memory device having lowered bit line resistance
A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on...
US-9,496,274 Three-dimensional non-volatile memory device
A memory device includes a stack of material layers with a plurality of NAND strings extending through the stack, and a trench through the stack with a pair of...
US-9,496,273 Three-dimensional nonvolatile memory device
A semiconductor device includes word lines stacked in a cell region of a substrate and each of the word lines includes a first conductive layer. At least one...
US-9,496,272 3D memory having NAND strings switched by transistors with elongated polysilicon gates
A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different...
US-9,496,271 3DIC system with a two stable state memory and back-bias region
A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of...
US-9,496,270 High density single-transistor antifuse memory cell
Various methods and devices that involve single transistor diode connected anti-fuse memory cells are disclosed. An exemplary memory cell comprises a thin gate...
US-9,496,269 Static random access memory
An SRAM unit cell includes first to fourth fin structures. A first Fin FET is formed by a first gate electrode and a first fin structure. A second Fin FET is...
US-9,496,268 Integrated circuits with asymmetric and stacked transistors
Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also...
US-9,496,267 Method for manufacturing semiconductor device
In one device, a first space partitioned by first and second line patters is filled with a multilayer film that is composed of a first silicon film having a...
US-9,496,266 Semiconductor device including a capacitor and a method of manufacturing the same
A method of manufacturing a semiconductor device is provided. The method includes sequentially forming a mold layer and a preliminary support layer on a...
US-9,496,265 Circuit and system of a high density anti-fuse
A high density anti-fuse cell can be built at the cross points of two perpendicular interconnect lines, such as active region lines, active and polysilicon...
US-9,496,264 Structure and formation method of FinFET device
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a...
US-9,496,263 Stacked strained and strain-relaxed hexagonal nanowires
A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and...
US-9,496,262 High mobility transistors
An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity...
US-9,496,261 Low power semiconductor transistor structure and method of fabrication thereof
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced .sigma.V.sub.T...
US-9,496,260 Tall strained high percentage silicon germanium fins for CMOS
A silicon germanium alloy (SiGe) fin having a first germanium content is provided within first and second device regions. Each SiGe fin is located on a...
US-9,496,259 FinFET semiconductor device having fins with stronger structural strength
A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending...
US-9,496,258 Semiconductor fin isolation by a well trapping fin portion
A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a...
US-9,496,257 Removal of semiconductor growth defects
After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material...
US-9,496,256 Semiconductor device including a vertical gate-all-around transistor and a planar transistor
A semiconductor device includes a first transistor and a second transistor. Each of the first and second transistors includes a channel. The channel of the...
US-9,496,255 Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer....
US-9,496,254 Capacitor using middle of line (MOL) conductive layers
A method for fabricating a metal-insulator-metal (MIM) capacitor includes depositing a first middle of line (MOL) conductive layer over a shallow trench...
US-9,496,253 Miniature passive structures, high frequency electrostatic discharge protection networks, and high frequency...
According to various embodiments, a miniature passive structure for electrostatic discharge protection and input/output matching for a high frequency integrated...
US-9,496,252 ESD protection device with improved bipolar gain using cutout in the body well
An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base...
US-9,496,251 Electrostatic discharge protector
The present invention provides electrostatic discharge protectors. One aspect of the present invention provides an electrostatic discharge protector includes a...
US-9,496,250 Tunable scaling of current gain in bipolar junction transistors
Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined...
US-9,496,249 3DIC package and methods of forming the same
A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding...
US-9,496,248 Interposer for integrated circuit chip package
An interposer for an electronic circuit chip package may include a substrate, a recess, first conductive vias, and second conductive vias. The substrate may...
US-9,496,247 Integrated camera module and method of making same
A camera module and method of making same, includes a substrate of conductive silicon having top and bottom surfaces, a sensor device, and an LED device. The...
US-9,496,246 Light emitting diode package and method for manufacturing same
An LED packaging includes a substrate having a top surface and a bottom surface opposite to the top surface, a recess defined in the top surface, an LED mounted...
US-9,496,245 Semiconductor package with integrated semiconductor devices and passive component
According to one exemplary embodiment, a semiconductor package includes a substrate having lower and upper surfaces. The semiconductor package further includes...
US-9,496,244 Light emitting module and light irradiating apparatus
A light emitting module includes: a substrate; at least one light emitting element line including a plurality of light emitting elements that are arrayed on the...
US-9,496,243 Microelectronic assembly with opposing microelectronic packages each having terminals with signal assignments...
A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face...
US-9,496,242 Stackable microelectronic package structures
A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon....
US-9,496,241 Integrated circuit packaging for implantable medical devices
A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part,...
US-9,496,240 Systems and methods for optimizing looping parameters and looping trajectories in the formation of wire loops
A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to...
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