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Nitride-enriched oxide-to-oxide 3D wafer bonding
A semiconductor structure comprising a first semiconductor structure; a second semiconductor structure; and a silicon-nitride layer configured to bond the first...
Sloped bonding structure for semiconductor package
A bonding structure includes a substrate having a top surface and including at least one bonding pad. Each bonding pad is disposed adjacent to the top surface...
Semiconductor device having solderable and bondable electrical contact
A semiconductor device includes a semiconductor chip and a plurality of electrical contact pads disposed on a main face of the semiconductor chip, wherein the...
A microelectronic assembly includes first and second surfaces, a first thin conductive element, a first conductive projection, and a first fusible mass. The...
Pillar design for conductive bump
A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches...
Wafer-level chip-scale package structure utilizing conductive polymer
An integrated conductive polymer-solder ball structure is provided. The integrated conductive polymer-solder ball structure comprises a sputter seed layer...
Interconnection structure and method of forming same
An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically...
Semiconductor device and its manufacturing method
The present invention makes it possible to: reduce the manufacturing cost of a semiconductor device having a redistribution layer; and further improve the...
Bypass ring to improve noise isolation of coils and inductors
An integrated circuit (IC) comprises a plurality of metal layers; a seal ring arranged around a perimeter of the IC and included in at least a portion of the...
Light sensitive switch for semiconductor package tamper detection
Embodiments relate to the detection of semiconductor tampering with a light-sensitive circuit. A tamper detection device for an integrated circuit includes a...
Transient electronic devices comprising inorganic or hybrid inorganic and
organic substrates and encapsulates
The invention provides transient devices, including active and passive devices that physically, chemically and/or electrically transform upon application of at...
Integrated circuit and method of manufacturing an integrated circuit
In various embodiments, an integrated circuit is provided. The integrated circuit may include a semiconductor chip and an electrically conductive composite...
Semiconductor-on-insulator with back side support layer
In one embodiment, an integrated circuit with a signal-processing region is disclosed. The integrated circuit comprises a silicon-on-insulator die singulated...
Semiconductor device, semiconductor package, and electronic device
A semiconductor device, a semiconductor package, and an electronic device are provided. The electronic device includes a first semiconductor package disposed on...
Recessed metal liner contact with copper fill
A method of fabricating a contact above a source or drain region of an integrated circuit includes depositing a first liner conformally in a bottom and along a...
Semiconductor device having air gap structures and method of fabricating
One method includes forming a conductive feature in a dielectric layer on a substrate. A first hard mask layer and an underlying second hard mask layer are...
Semiconductor devices including spacers
A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of...
Semiconductor device including insulating films with different moisture
resistances and fabrication method thereof
A semiconductor device has a structure including a substrate, a first insulating film formed over a part of a principal plane of the substrate, a conductive...
Method for forming fuse pad and bond pad of integrated circuit
The present disclosure relates to a method of fabricating a semiconductor device. A semiconductor device includes a bond pad and a fuse layer. The bond pad...
A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor formed in the multilayer interconnect, and a...
Semiconductor package including an antenna formed in a groove within a
A semiconductor package including an antenna formed integrally therewith. The semiconductor package includes: a semiconductor chip; a sealing part sealing the...
Integrated circuit device having through-silicon-via structure
An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device...
Method and apparatus of forming a via
The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a...
Semiconductor package including stacked semiconductor chips and a
Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second...
Transparent substrate having nano pattern and method of manufacturing the
Provided are a transparent substrate having a nano pattern, and a method of manufacturing the same, which enables the nano pattern to be easily formed on the...
Power electronics devices having thermal stress reduction elements
Power electronics devices having thermal stress reduction elements are disclosed. A power electronics device includes a heat source having a heat source...
Integrated device package comprising a magnetic core inductor with
protective ring embedded in a package substrate
An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg...
Substrate core via structure
By now it should be appreciated that there has been provided methods for making a packaged semiconductor device (and the resultant device) including a via layer...
Logic die and other components embedded in build-up layers
Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating...
Stackable package and method
A stackable package is placed within a mold during an encapsulation operation. A compliant surface, e.g., of a compliant film, of the mold is pressed down on...
High density organic bridge device and method
Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic...
Semiconductor device having compliant and crack-arresting interconnect
A power converter (300) has a first transistor chip (310) conductively stacked on top of a second transistor chip (320) attached to a substrate (301). A first...
Cascode semiconductor package and related methods
A semiconductor package includes an electrically conductive base (base) having a source connector. A drain connector and a gate connector are electrically...
Flippable leadframe for packaged electronic system having vertically
stacked chips and components
A leadframe (100) for electronic systems comprising a first sub-leadframe (110) connected by links (150) to a second sub-leadframe (120), the first and second...
Power semiconductor package
A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body,...
In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is...
Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side...
An electronic substrate includes: an electronic element provided on a first face of a semiconductor substrate having a through hole; a passive element provided...
Semiconductor device and method of manufacturing semiconductor device
According to one embodiment, a semiconductor device includes a first conductor, a second conductor, and an envelope. The first conductor includes a first...
Modular heat-transfer systems
Some modular heat-transfer systems can have an array of at least one heat-transfer element being configured to transfer heat to a working fluid from an operable...
Heat spreader with flexible tolerance mechanism
A semiconductor device packaging system includes a substrate, a heat spreader, a stiffener attached to the substrate, and at least one die electrically coupled...
Integration of backside heat spreader for thermal management
A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a...
Near junction cooling for GaN devices
Apparatus and methods are provided for heat removal and spreading from a field effect transistor (FET) including a substrate, a first source, a first gate, and...
Packages and methods of manufacture thereof
Packages and methods of manufacture thereof are described. In an embodiment, a package may include a first chip package and a die structure disposed over the...
Semiconductor device and method of depositing encapsulant along sides and
surface edge of semiconductor die in...
A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A...
Customized module lid
A method of forming a custom module lid. The method may include placing a multichip module (MCM) between a module base and a temporary lid, target components...
Semiconductor chip with structured sidewalls
A semiconductor chip includes a body having a frontside, a backside opposite the frontside, and sidewalls extending between the backside and frontside, at least...
Test pattern of semiconductor device
A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart...
A mask includes a substrate, an effective pixel formation region and a reference pattern formation region. A pixel pattern for forming a pixel component that...
Feedback of layer thickness timing and clearance timing for polishing
During polishing of a first substrate at a first polishing station, a sequence of measurements by a first in-situ monitoring system is monitored to determining...