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Patent # Description
US-9,496,189 Stacked semiconductor devices and methods of forming same
Stacked semiconductor devices and methods of forming the same are disclosed. First tier workpieces are mounted on a top surface of a semiconductor device to...
US-9,496,188 Soldering three dimensional integrated circuits
A method for soldering three-dimensional integrated circuits is provided. A three-dimensional integrated circuit is heated to a base temperature, wherein the...
US-9,496,187 Setup for multiple cross-section sample preparation
A multiple-sample-holder polishing setup for cross-section sample preparation and a method of making a device using the same are presented. The...
US-9,496,186 Uniform height tall fins with varying silicon germanium concentrations
A method of making a semiconductor device includes forming a first fin in a first semiconducting material layer disposed over a substrate, the first...
US-9,496,185 Dual channel finFET with relaxed pFET region
Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of...
US-9,496,184 III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology
In one aspect, a method of fabricating a bipolar transistor device on a wafer includes the following steps. A dummy gate is formed on the wafer, wherein the...
US-9,496,183 Selective thickening of pFET dielectric
A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial...
US-9,496,182 Semiconductor device and method for fabricating the same
A semiconductor device comprises a substrate, a semiconductor fin, a first isolation structure and a first dummy structure. The semiconductor fin comprises a...
US-9,496,181 Sub-fin device isolation
A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the...
US-9,496,180 Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) and the corresponding device are disclosed. A high-k/metal gate (HK/MG) and a conductive feature...
US-9,496,179 Method of manufacturing semiconductor devices
A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a...
US-9,496,178 Semiconductor device having fins of different heights and method for manufacturing the same
The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a...
US-9,496,177 Method and apparatus for plasma dicing a semi-conductor wafer
The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma...
US-9,496,176 Semiconductor device
A semiconductor device includes a semiconductor structure, a plurality of gate structures, at least one source/drain structure, at least one trench, a...
US-9,496,175 Semiconductor device, method of manufacturing the same and camera
A semiconductor device includes a substrate that has a cell and a peripheral area, and an insulating layer. The insulating layer includes a first region located...
US-9,496,174 Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via...
Integrated circuits and methods of manufacturing such circuits are disclosed herein that feature metal line-via matrix insertion after place and route processes...
US-9,496,173 Thickened stress relief and power distribution layer
An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a...
US-9,496,172 Method for forming interconnection structures
The present invention provides a method for forming interconnection structures, including the following steps: providing a semiconductor wafer with a dielectric...
US-9,496,171 Printed interconnects for semiconductor packages
A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package...
US-9,496,170 Interconnect having air gaps and polymer wrapped conductive lines
A method includes depositing a first polymer layer over a first dielectric layer, forming a first opening and a second opening using an etching process, wherein...
US-9,496,169 Method of forming an interconnect structure having an air gap and structure thereof
A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first...
US-9,496,168 Semiconductor package with via-coupled power transistors
In one implementation, a semiconductor package includes a carrier including first and second conductive segments, and first and second transistors attached...
US-9,496,167 Integrated bit-line airgap formation and gate stack post clean
Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called "2-d flat cell"...
US-9,496,166 Substrate transferring arm and substrate transferring apparatus including the same
A substrate transporting arm and a substrate transporting apparatus to prevent a substrate from sliding and increase a process speed of the substrate, thereby...
US-9,496,165 Method of forming a flexible semiconductor layer and devices on a flexible carrier
A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a...
US-9,496,164 Cyclic olefin polymer compositions and polysiloxane release layers for use in temporary wafer bonding processes
The invention broadly relates to cyclic olefin polymer bonding compositions and release compositions, to be used independently or together, that enable thin...
US-9,496,163 Carrier and method of fabricating semiconductor device using the same
Provided are a carrier and a method of fabricating a semiconductor device using the same. The carrier may include a recess region provided adjacent to an edge...
US-9,496,162 Method for supplying inert gas to STB in semiconductor wafer production system and semiconductor wafer...
A method for supplying inert gas to a side track buffer (STB) in a semiconductor wafer production system includes a step of sensing that a front opening unified...
US-9,496,161 Methods and devices for securing and transporting singulated die in high volume manufacturing
A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database,...
US-9,496,160 Workpiece orienting and centering with a factory interface
A workpiece orientation is determined by camera during transfer to a load lock, and the orientation is corrected during load lock pump down.
US-9,496,159 Wafer position correction with a dual, side-by-side wafer transfer robot
Methods and systems for positioning wafers using a dual side-by-side end effector robot are provided. The methods involve performing place moves using dual...
US-9,496,158 Processing apparatus
Provided is a processing apparatus for performing a processing of a substrate to be processed using a high-pressure fluid to prevent the generation of particles...
US-9,496,157 Ultraviolet curing apparatus having top liner and bottom liner made of low-coefficient of thermal expansion...
An ultraviolet curing apparatus includes a chamber, a gas flow generator, and an ultraviolet lamp. The gas flow generator includes a top liner and a bottom...
US-9,496,156 Semiconductor crystal body processing method and semiconductor crystal body processing device
A semiconductor crystal body processing method includes providing a semiconductor crystal body, sandwiching the semiconductor crystal body between a pair of...
US-9,496,155 Methods of selectively transferring active components
A method for selectively transferring active components (22) from a source substrate (20) to a destination substrate (10) includes providing a source substrate...
US-9,496,154 Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to...
A microelectronic component (110, 120) has a contact pad (110C, 120C, 920C) recessed in a cavity (410) and covered by underfill tape (130). The cavity has a...
US-9,496,153 Semiconductor device and method of manufacturing the same
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a...
US-9,496,152 Carrier system with multi-tier conductive posts and method of manufacture thereof
A method of manufacture of a carrier system includes: providing a carrier base; forming a recess in the carrier base with the recess around a planar surface;...
US-9,496,151 Semiconductor device and semiconductor device manufacturing method
In aspects of the invention, an n-type epitaxial layer that forms an n.sup.- type drift layer is formed on the upper surface of an n-type semiconductor...
US-9,496,150 Etching processing method
An etching processing method for etching a substrate formed with a target film and a mask film is performed in a substrate processing apparatus including a...
US-9,496,149 Semiconductor devices and methods for manufacturing the same
Semiconductor devices and methods for manufacturing the same are disclosed. In an embodiment, a method of manufacturing a semiconductor device may include...
US-9,496,148 Method of charge controlled patterning during reactive ion etching
A method of reactive ion etching a wafer includes providing a plasma processing tool having a wafer chuck within a chamber and an electrode creating a plasma...
US-9,496,147 Plasma processing apparatus and plasma processing method
In a plasma processing apparatus comprising a processing chamber arranged in a vacuum chamber, a sample stage arranged under the processing chamber and having...
US-9,496,146 Method for forming through-base wafer vias
Method for manufacturing semiconductor wafers having at least one through-base wafer via, the said method comprising the steps of (1) providing a semiconductor...
US-9,496,145 Electrochemical plating methods
An electrochemical process for applying a conductive film onto a substrate having a seed layer includes placing the substrate into contact with an...
US-9,496,144 Method of fabricating a charge-trapping gate stack using a CMOS process flow
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a...
US-9,496,143 Metal gate structure for midgap semiconductor device and method of making same
A PFET-based semiconductor gate structure providing a midgap work function for threshold voltage control between that of a NFET and a PFET is created by...
US-9,496,142 Dummy gate placement methodology to enhance integrated circuit performance
A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an...
US-9,496,141 Device including quantum dots
A method of making a device comprises forming a layer comprising quantum dots over a substrate including a first electrode, fixing the layer comprising quantum...
US-9,496,140 Silicon wafer based structure for heterostructure solar cells
A multi-junction photovoltaic device includes a silicon substrate and a dielectric layer formed on the silicon substrate. A germanium layer is formed on the...
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