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Patent # Description
US-9,496,038 Three-dimensional flash memory device including dummy word line
A three-dimensional flash memory device includes a plurality of cell strings arranged in a direction perpendicular to a substrate. The three-dimensional flash...
US-9,496,037 Memory circuit
A memory circuit includes: a bistable circuit (30) that writes data; nonvolatile elements (MTJ1, MTJ2) that store the data written in the bistable circuit into...
US-9,496,036 Writing method for resistive memory cell and resistive memory
A writing method for a resistive memory cell and a resistive memory are provided. The writing method includes following steps. A reference voltage is provided...
US-9,496,035 Devices and methods to program a memory cell
Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell.
US-9,496,034 Memory device with a common source line masking circuit
A memory device comprising a plurality of memory tiles, each tile comprising a local common source line (CSL) plate, a plurality of bitlines and a plurality of...
US-9,496,033 Method and system of programmable resistive devices with read capability using a low supply voltage
A Programmable Resistive Device (PRD) memory that can be read under low voltage is disclosed. The PRD includes at least one Programmable Resistive Element (PRE)...
US-9,496,032 Variable resistive memory device including controller for driving bitline, word line, and method of operating...
A variable resistive memory device may include a memory region and controller. The memory region may include a plurality of unit memory cells each electrically...
US-9,496,031 Method and apparatus for faster determination of a cell state of a resistive memory cell using a parallel resistor
A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states comprising a sensing circuit, a...
US-9,496,030 Resistive memory device implementing selective memory cell refresh
A resistive memory device implements a selective refresh operation in which only memory cells with reduced sense margin are refreshed. In some embodiments, the...
US-9,496,029 6T bitcell for dual port SRAM memories with single-ended read and single-ended write and optimized bitcells for...
Described herein is a 6T bitcell for dual port SRAM that performs single ended read and single ended write. The bitcell and architecture does not have either a...
US-9,496,028 Semiconductor memory device that can stably perform writing and reading without increasing current consumption...
Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage...
US-9,496,027 Static random access memory device including write assist circuit and writing method thereof
A static random access memory device may include a write driver configured to float one of a first bitline and a second bitline connected to a memory cell and...
US-9,496,026 Memory device with stable writing and/or reading operation
A memory device includes a first inverter, a second inverter cross-coupled with the first inverter, an accessing unit, and a switching unit. The accessing unit...
US-9,496,025 Tunable negative bitline write assist and boost attenuation circuit
An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes...
US-9,496,024 Automatic latch-up prevention in SRAM
A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank...
US-9,496,023 Comparison operations on logical representations of values in memory
One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first...
US-9,496,022 Semiconductor device including power management unit for refresh operation
To provide a novel semiconductor device. The semiconductor device includes a circuit including a memory cell including a transistor using an oxide...
US-9,496,021 Power reduction in thyristor random access memory
Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various...
US-9,496,020 Six-transistor thyristor SRAM circuits and methods of operation
A memory cell based upon cross-coupled thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select...
US-9,496,019 CMOS analog memories utilizing ferroelectric capacitors
A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a...
US-9,496,018 Nonvolatile memory interface for metadata shadowing
A memory includes non-volatile memory devices, each of which has multiple nonvolatile memory cells. A write controller streams bits to the memory devices in...
US-9,496,017 Memory cell with schottky diode
Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode...
US-9,496,016 Memory cell and memory device having the same
A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization...
US-9,496,015 Array structure having local decoders in an electronic device
An array structure includes: a plurality of first signal lines and a plurality of sub-arrays. Each of the sub-array includes: a second signal line, a plurality...
US-9,496,014 Random access memory and memory access method thereof
The present invention discloses a random access memory and the memory access method thereof capable of avoiding read disturbance and increasing reading speed....
US-9,496,013 Semiconductor device and operating method thereof
A semiconductor device includes memory blocks including a plurality of strings in which memory cells are coupled between select transistors; a peripheral...
US-9,496,012 Method and apparatus for reference voltage calibration in a single-ended receiver
According to at least one example embodiment, a method and corresponding system, or circuit, for calibrating a reference voltage of a single-ended receiver,...
US-9,496,011 Semiconductor memory device, memory system including the same and operating method thereof
A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in...
US-9,496,010 Semiconductor device and memory system including the same
A semiconductor device and a memory system including the same are disclosed, which relate to a technology for reducing a toggle current of a global input output...
US-9,496,009 Memory with bank-conflict-resolution (BCR) module including cache
A memory device includes a block of memory cells and a cache. The block of memory cells is a random access memory with multiple ports. The block of memory cells...
US-9,496,008 Determination of a common mode voltage
The invention relates to a receiving unit for performing a calibration of a reference voltage, comprising a reference voltage unit for generating and applying a...
US-9,496,007 Method and apparatus for generating piece-wise linear regulated supply
The disclosure provides a voltage regulator for generating piece-wise linear regulated supply voltage. The voltage regulator includes a first clamp circuit that...
US-9,496,006 Memory module and memory controller for controlling a memory module
The memory module having a plurality of memory chips and a plurality of connections for connecting the memory module to a processor. At least part of the...
US-9,496,005 Electronic apparatus, display control method and program for displaying an image for selecting a content item...
An electronic apparatus includes an operation reception unit that receives a switching operation for switching between a list display screen where index images...
US-9,496,004 Method and apparatus for dividing and displaying contents
A method for dividing and displaying a content unit includes: extracting a sub-content unit which is generated by dividing an original content unit by a preset...
US-9,496,003 System and method for playlist generation based on similarity data
Methods and arrangements for facilitating media playlist generation for a program participant based at least in part on media library inventory information...
US-9,496,002 Image processing apparatus, image processing method, and recording medium
The present invention comprises an input part for inputting image data, a receiving part for receiving production information relating to production transmitted...
US-9,496,001 Video processing apparatus and method of controlling video processing apparatus
A frame memory of a video processing apparatus stores video frames that are respectively compressed based on compression parameters. A video output unit outputs...
US-9,496,000 Audio modification for adjustable playback rate
Features described herein relate to providing the capability to playback audiovisual content in a comprehensible manner at a rate adjustable by the viewer. For...
US-9,495,999 Phase error detector and optical disc device
A phase error detector includes a sine wave generation circuit that generates a sine wave signal, based on a first input signal of a first period, a cosine wave...
US-9,495,998 Information recording and/or reproducing apparatus
Contents data that have been enciphered and transmitted are recorded as they are on a recording medium, and the contents key used to encipher these data is...
US-9,495,997 System and method for dynamic enablement of storage media associated with an access controller
Systems and methods for reducing problems and disadvantages associated traditional approaches to provisioning using access controllers are disclosed. A method...
US-9,495,996 Writer with increased write field
A writer includes a magnetic write pole having a leading surface and a trailing surface and a near field transducer peg spaced from the leading surface of the...
US-9,495,995 Adjusting laser power to achieve equivalent track spacing for paired heads that simultaneously write to a...
A relatively larger nominal track spacing associated with a first write head is determined and a relatively smaller nominal track spacing associated with a...
US-9,495,994 Optical disc capable of recording address information with the same modulation on sides of adjacent grooves
An optical disc medium includes a land and a groove at which information can be recorded. A predetermined number of address information units which record...
US-9,495,993 Holographic device and method for data reading using the same
A holographic device includes a holographic storage device, a shearing interferometer, and an optical receiver. The holographic storage device is configured to...
US-9,495,992 Holographic data reproduction apparatus and method thereof
A holographic data reproduction apparatus is provided. The holographic data reproduction apparatus includes: a charged-coupled device (CCD) that photographs...
US-9,495,991 Method for forming silicon oxide and metal nanopattern's, and magnetic recording medium for information storage...
The present invention relates to a method for forming a silicon oxide nanopattern, in which the method can be used to easily form a nanodot or nanohole-type...
US-9,495,990 Hard magnetic exchange-coupled composite structures and perpendicular magnetic recording media including the same
Hard magnetic exchange-coupled composite structures and perpendicular magnetic recording media including the hard magnetic exchange-coupled composite...
US-9,495,989 Laminating magnetic cores for on-chip magnetic devices
A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a...
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