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Interference cancellation in microwave backhaul systems
A first microwave backhaul assembly comprises a first antenna, a front-end circuit, an inter-backhaul-assembly interface circuit, and an interference...
Receiver and receiving method of receiver
It is determined, on the basis of a signal component of a low frequency band and a signal component of a desired channel band of an intermediate frequency...
Sliding intermediate frequency (IF) receiver with adjustable division
ratio and sliding IF reception method
A sliding intermediate frequency (IF) receiver and a sliding IF reception method are provided. A first local oscillation signal and a second local oscillation...
Methods and apparatus for adapting transmitter configuration for efficient
concurrent transmission and radar...
Certain aspects of the present disclosure relate to adapting transmitter configuration for efficient concurrent primary user detection through adaptive...
Low noise detection system using log detector amplifier
A low noise detection system is disclosed in which a modulator located in a transmitter or a receiver is configured to convert a voltage data signal to a...
Wireless communication apparatus, communication control method, and
computer-readable recording medium
A wireless communication apparatus includes an amplifying unit that amplifies an input signal that includes signals with different frequencies of a first...
Antenna for receiving and/or transmitting polarized communication signals
An antenna for communicating with a remote communication system. The antenna comprises main and sub reflectors, a beam shaping element facing the sub reflector...
Signal transmitter, message generating system and signal power adjusting
A signal transmitter with adjustable signal power includes a housing, a first adjustable metal shielding layer and a circuit board. The first adjustable metal...
Interference control between different radio communication systems
involving user equipments
A first User Equipment (UE), a second UE, a first Radio Network Node (RNN), and methods therein for controlling interference between transmissions in a first...
Data deduplication with adaptive erasure code redundancy
Example apparatus and methods combine erasure coding with data deduplication to simultaneously reduce the overall redundancy in data while increasing the...
ECC polar coding and list decoding methods and codecs
A method of decoding data encoded with a polar code and devices that encode data with a polar code. A received word of polar encoded data is decoded following...
Modified trellis-based min-max decoder for non-binary low-density
parity-check error-correcting codes
A decoder includes a syndrome value calculator configured to generate multiple syndrome values. The decoder further includes a check node to variable node...
Method and apparatus for decoding low-density parity-check code
Provided is a method of decoding a low-density parity-check code (LDPC). The decoding method including an initialization process, a check node update process, a...
Random access to compressed data using bitwise indices
Methods and apparatus are provided for random access to compressed data using bitwise indices, enabling interaction with compressed data as if interaction were...
Hardware data compressor that sorts hash chains based on node string match
A hardware data compressor. A first hardware engine scans an input block of characters and uses a plurality of lists of nodes to produce back pointers to...
Very high dynamic-range switched capacitor ADC with large input impedance
for applications tolerating increased...
A modulator is configured to respond to input swings by providing a feedback voltage via a feedback path to compromise an increase in noise and distortion power...
Signal dependent subtractive dithering
A sigma-delta modulator circuit selectively removes a dither signal previously added to an input of a quantizer circuit from the quantizer circuit output when...
Common mode sampling mechanism for residue amplifier in switched current
pipeline analog-to-digital converters
A switched current pipeline analog-to-digital converter (ADC) integrated circuit. The integrated circuit comprises a track and hold circuit (T/H) and a residue...
Multiplying analog to digital converter and method
A multiplying analog to digital converter (ADC) including a successive-approximation-register (SAR) analog to digital converter (ADC) having a sample input and...
Semiconductor device comprising analog to digital converters sharing
reference capacitor and system on chip...
Provided are a semiconductor device and a System on Chip (SoC). The semiconductor device includes a reference capacitor that receives a reference voltage from a...
Efficient calibration of errors in multi-stage analog-to-digital converter
Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate...
Circuit for and method of implementing a time-interleaved
A circuit for implementing a time-interleaved analog-to-digital converter is described. The circuit comprises a sampling clock generator configured to receive a...
Time interleaving structure for a multi-lane analog-to-digital converter
A multi-lane analog to digital converter (ADC) samples an analog input according to multiple phases of a sampling clock. Ideally, the multiple phases of the...
Apparatus for offset trimming and associated methods
Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a...
Non-linearity cancellation in a dual-path ADC
The overall performance of a dual-path ADC system may be improved by using a VCO-based ADC for small-amplitude signals and employing non-linear cancellation to...
An atomic oscillator using a quantum interference effect, includes: a first light source unit emitting first light which includes a resonant light pair having...
Gas cell, quantum interference device, atomic oscillator, electronic
device, and moving object
A gas cell includes an internal space in which metal atoms and a buffer gas are sealed, the buffer gas includes nitrogen gas, and the partial pressure of the...
Apparatus and methods for synchronizing phase-locked loops
Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a...
Oscillation circuit, oscillator, electronic device, and moving object
An oscillation circuit, an oscillator, an electronic device, and a moving object which are capable of adjusting an output frequency in a high modulation...
Closed loop bank selection for temperature compensation in wireless
The disclosure is directed to compensating for frequency drift in a voltage-controlled oscillator (VCO). Example methods and systems are described which may...
Frequency-locked voltage regulated loop
An integrated circuit includes a frequency-locked voltage regulated loop that further includes a voltage controlled oscillator (VCO), a frequency divider that...
Phase frequency detector (PFD) circuit with improved lock time
Described examples include circuitry and methods to control lock time of a phase lock loop (PLL) or other locking circuit, in which a phase frequency detector...
Low power loss of lock detector
A loss of lock detector that includes a logic gate, a voltage-to-current converter coupled to the logic gate, a capacitor coupled to the converter, and a...
Phase locked loop with a frequency multiplier and method of configuring
the phase locked loop
A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically...
Synchronization for multiple arbitrary waveform generators
A system and method synchronizes multi-AWG system, where such systems are of a type having a master arbitrary waveform generator (AWG), one or more slave AWGs,...
Phase locked loop circuit
A phase locked loop circuit includes a first current source that outputs a current from a first output node. The phase locked loop circuit includes a driving...
Digitally reconfigurable ultra-high precision internal oscillator
A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a...
Temperature compensated crystal oscillator
The temperature compensated crystal oscillator has a rectangular substrate, a frame which is provided on an upper surface of the substrate, a mounting frame...
Current-feedback operational amplifier-based sinusoidal oscillator
The current-feedback operational amplifier-based sinusoidal oscillator circuit includes a pair of CFOAs connected to each other using five resistors and two...
Analog circuits incorporating magnetic logic units
A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line...
Multiple-layer configuration storage for runtime reconfigurable systems
The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more...
Space-multiplexing DRAM-based reconfigurable logic
According to one general aspect, an apparatus may include a random access memory array that, in turn, includes a reconfigurable look-up table. The ...
Programmable logic device virtualization
A device includes a programmable logic fabric. The programmable logic fabric includes a first area, wherein a first persona is configured to be programmed in...
Virtualization of programmable integrated circuits
A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources,...
Mixed-radix and/or mixed-mode switch matrix architecture and integrated
circuit, and method of operating same
An integrated circuit comprising a plurality of logic tiles, wherein each logic tile includes a plurality of (i) computing elements and (ii) switch matrices....
Wordline decoder circuits for embedded charge trap
Wordline decoder circuits for an embedded Multi-Time-Read-Only-Memory that includes a plurality of NMOS memory cells coupled to a plurality of wordlines in each...
High speed level translator
A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a...
Integrated circuit having multiple identified identical blocks
An integrated circuit comprising N adjacent identical blocks indexed by index j, a current block connected to preceding and following blocks, each comprising...
Method and control device for recovering NBTI/PBTI related parameter
degradation in MOSFET devices
The invention provides a method for recovering NBTI/PBTI related parameter degradation in MOSFET devices. The method includes operating the at least one MOSFET...
Method of driving semiconductor device
A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power...