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Patent # Description
US-9,502,583 Complementary high mobility nanowire neuron device
A method for forming a semiconductor device includes providing a substrate structure, which includes a nanowire structure supported by two isolation regions on...
US-9,502,582 Non-volatile memory unit and method for manufacturing the same
A non-volatile memory unit includes a substrate, a first dielectric layer, an erase gate, a floating gate, a second dielectric layer, a coupled dielectric layer...
US-9,502,581 Non-volatile floating gate memory cells
A storage transistor for non-volatile memory can be fabricated to create controlled sharp polycrystalline silicon (polysilicon) edges. The edges concentrate the...
US-9,502,580 Semiconductor device and method for manufacturing the same
A highly reliable semiconductor device exhibiting stable electrical characteristics is provided. Further, a highly reliable semiconductor device is provided....
US-9,502,579 Thin film transistor substrate
A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the...
US-9,502,577 Oxide thin film transistor, display device, and method for manufacturing array substrate
Provided are oxide thin-film transistor and display device employing the same, and method for manufacturing an oxide thin-film transistor array substrate. A...
US-9,502,576 Thin film transistor and method for manufacturing the same, array substrate, display device
There are provided a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor is formed on a...
US-9,502,575 Oxide thin film transistor array substrate having transparent connection structure connecting source electrode...
An oxide thin film transistor array substrate, a manufacturing method thereof and a display panel are provided. The oxide TFT array substrate includes a base...
US-9,502,574 Thin film transistor and manufacturing method thereof
A thin film transistor includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and a pair of source...
US-9,502,573 Pixel structure and method of manufacturing a pixel structure
A pixel structure and a method of manufacturing a pixel structure are provided. The pixel structure includes an active device, a gate insulation layer, a...
US-9,502,572 Bottom-gate transistor including an oxide semiconductor layer contacting an oxygen-rich insulating layer
A highly reliable semiconductor device which includes a transistor including an oxide semiconductor is provided. In a semiconductor device including a...
US-9,502,571 Thin film layer and manufacturing method thereof, substrate for display and liquid crystal display
A thin film layer and manufacturing method thereof, a substrate for display and a liquid crystal display are provided. The embodiments according to the present...
US-9,502,570 Thin film transistor and manufacturing method thereof, an array substrate and a display device
Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate and a display device, to improve the...
US-9,502,569 FinFET structure and manufacture method
A method for forming a FinFET transistor structure includes providing a substrate with a buried oxide layer and a layer of first semiconductor material. One or...
US-9,502,568 Non-planar quantum well device having interfacial layer and method of forming same
Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V...
US-9,502,567 Semiconductor fin structure with extending gate structure
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the...
US-9,502,566 Method for producing a field effect transistor including forming a gate after forming the source and drain
The invention concerns a method for producing a transistor. The gate of the transistor is produced after having produced source and drain electrodes of the...
US-9,502,565 Channel strain control for nonplanar compound semiconductor devices
A circuit device having differently-strained NMOS and PMOS FinFETs is provided. In an exemplary embodiment, a semiconductor device includes a substrate with a...
US-9,502,564 Fully depleted device with buried insulating layer in channel region
A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions...
US-9,502,563 Semiconductor device having embedded strain-inducing pattern and method of forming the same
In a semiconductor device, a first active region has a first .SIGMA.-shape, and the second active region has a second .SIGMA.-shape. When a line that is...
US-9,502,562 Fin field effect transistor including self-aligned raised active regions
Fin mask structures are formed over a semiconductor material portion on a crystalline insulator layer. A disposable gate structure and a gate spacer are formed...
US-9,502,561 Semiconductor devices and methods of forming the same
An embodiment is a semiconductor device, comprising: a substrate; a plurality of fin structures disposed on the substrate; a plurality of first strained...
US-9,502,560 Semiconductor device and method of manufacturing the same
Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a substrate having a well formed therein, the well...
US-9,502,559 Dislocation stress memorization technique (DSMT) on epitaxial channel devices
The present disclosure relates to method of forming a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM)...
US-9,502,558 Local strain generation in an SOI substrate
Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in...
US-9,502,557 LDMOS for high frequency power amplifiers
An LDMOSFET is designed with dual modes. At the high voltage mode, it supports a high breakdown voltage and is biased at a high voltage to get the benefits of...
US-9,502,556 Integrated fabrication of semiconductor devices
In a method for manufacturing a semiconductor device, a substrate including a gate structure is provided. A source region and a drain region are formed at...
US-9,502,555 Semiconductor device and fabricating method thereof
A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes: a substrate comprising a trench; a first electrode...
US-9,502,554 High frequency switching MOSFETs with low output capacitance using a depletable P-shield
Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The...
US-9,502,553 Semiconductor device and method for manufacturing the same
In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper...
US-9,502,552 Silicon carbide semiconductor device
There is provided a silicon carbide semiconductor device having an improved switching characteristic. A MOSFET includes a silicon carbide layer, a gate...
US-9,502,551 Nitride semiconductor transistor device
A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film...
US-9,502,550 High electron mobility semiconductor device and method therefor
In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate...
US-9,502,549 Nitride semiconductor device
A nitride semiconductor device includes the followings. A semiconductor multilayer structure is above a substrate and includes a first nitride semiconductor...
US-9,502,548 Semiconductor device
A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a gate electrode, a field plate, a first passivation layer,...
US-9,502,547 Charge reservoir IGBT top structure
An IGBT device may be formed from a substrate including a bottom semiconductor layer of a first conductivity and an upper semiconductor layer of a second...
US-9,502,546 Semiconductor device and semiconductor device manufacturing method
A semiconductor device and manufacturing method achieve miniaturization, prevent rise in threshold voltage and on-state voltage, and prevent decrease in...
US-9,502,545 Field effect semiconductor device
In order to reduce the source resistance in a field effect semiconductor device, an electron injection layer, which causes a band-to-band tunnel current to flow...
US-9,502,544 Method and system for planar regrowth in GaN electronic devices
A vertical JFET includes a III-nitride substrate and a III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The first...
US-9,502,543 Method of manufacturing for memory transistor with multiple charge storing layers and a high work function gate...
Methods of fabricating a memory device are described. Generally, the method begins with forming a tunnel dielectric layer over a channel region formed from a...
US-9,502,542 FinFET transistor with fin back biasing
A FinFET having fin back biasing and methods of forming the same are disclosed. The FinFET includes a substrate and a fin over the substrate. The fin includes a...
US-9,502,541 Forming fins on the sidewalls of a sacrificial fin to form a FinFET
A fin structure for a fin field effect transistor (FinFET) device is provided. The device includes a substrate, a first semiconductor material disposed on the...
US-9,502,540 Uniform height tall fins with varying silicon germanium concentrations
A method of making a semiconductor device includes forming a first fin in a first semiconducting material layer disposed over a substrate, the first...
US-9,502,539 FINFET device having a channel defined in a diamond-like shape semiconductor structure
The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the...
US-9,502,538 Structure and formation method of fin-like field effect transistor
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over...
US-9,502,537 Method of selectively removing a region formed of silicon oxide and plasma processing apparatus
Provided is a method of selectively removing a first region from a workpiece which includes the first region formed of silicon oxide and a second region formed...
US-9,502,536 Manufacturing method of thin film transistor display panel
Provided is a manufacturing method of a thin film transistor array panel including: formation of a gate line including a gate electrode on a substrate;...
US-9,502,535 Semiconductor structure and etch technique for monolithic integration of III-N transistors
Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A...
US-9,502,534 Preparation method for power diode
A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the...
US-9,502,533 Silicon recess etch and epitaxial deposit for shallow trench isolation (STI)
Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the...
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