Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,502,432 Semiconductor device comprising a slit insulating layer configured to pass through a stacked structure
The semiconductor device may include a substrate including a trench. The semiconductor device may include an isolation layer formed in the trench and including...
US-9,502,431 Nonvolatile semiconductor memory device and method of manufacturing the same
According to one embodiment, a memory device includes a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, . ....
US-9,502,430 Semiconductor integrated circuit device and a method of manufacturing the same
A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first...
US-9,502,429 Set of stepped surfaces formation for a multilevel interconnect structure
A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench...
US-9,502,428 Sidewall assisted process for wide and narrow line formation
A method of forming narrow and wide lines includes forming mandrels separated by wider gaps and narrower gaps, forming sidewall spacers on sides of the gaps,...
US-9,502,427 Non-volatile memory device and method of manufacturing the same
A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is...
US-9,502,426 One time programming non-volatile memory cell
A one time programming non-volatile memory cell includes a first floating gate transistor with a single gate structure, an isolation transistor, and a select...
US-9,502,425 Semiconductor device and method of manufacturing the same
The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation...
US-9,502,424 Integrated circuit device featuring an antifuse and method of making same
One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region,...
US-9,502,423 Semiconductor device layout and method for forming the same
A semiconductor includes a gate line having a first portion in a transistor region and a second portion in a decoupling capacitor region.
US-9,502,422 Electromechanical nonvolatile memory
A semiconductor device includes an insulating layer on a semiconductor substrate, a bit line including TiAl and disposed on the insulating layer, a sidewall...
US-9,502,421 Semiconductor device and method for fabricating a semiconductor device
A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials...
US-9,502,420 Structure and method for highly strained germanium channel fins for high mobility pFINFETs
A method is provided that includes providing a material stack of, from bottom to top, a relaxed and n-type doped silicon germanium alloy layer and a relaxed...
US-9,502,419 Structure for FinFETs
A FinFET device comprises a well over a substrate, an isolation region over the well and a fin line over the well and surrounded by the isolation region,...
US-9,502,418 Semiconductor devices with sidewall spacers of equal thickness
Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a...
US-9,502,417 Semiconductor device having a substrate including a first active region and a second active region
A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active...
US-9,502,416 Semiconductor device including transistors having different threshold voltages
A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a...
US-9,502,415 Method for providing an NMOS device and a PMOS device on a silicon substrate and silicon substrate comprising...
The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS)...
US-9,502,414 Adjacent device isolation
An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a...
US-9,502,413 Semiconductor devices including raised source/drain stressors and methods of manufacturing the same
A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a...
US-9,502,412 Semiconductor device structure with gate spacer having protruding bottom portion and method for forming the same
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack...
US-9,502,411 Strained finFET device fabrication
A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a...
US-9,502,410 Semiconductor structure and manufacturing method thereof
The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a...
US-9,502,409 Multi-gate semiconductor devices
A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including...
US-9,502,408 FinFET device including fins having a smaller thickness in a channel region, and a method of manufacturing same
A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate to a first thickness, forming a...
US-9,502,407 Integrating a planar field effect transistor (FET) with a vertical FET
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a...
US-9,502,406 Semiconductor device and method of fabricating the same
Provided is a semiconductor device and method of fabricating the same. The device includes a substrate including a first region and a second region, a first...
US-9,502,405 Semiconductor device with authentication code
A plurality of contact trenches are formed in a semiconductor structure. The plurality of contact trenches are formed with a contact opening width selected to...
US-9,502,404 Epitaxial formation mechanisms of source and drain regions
The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown...
US-9,502,403 Method for core and in/out-put device reliability improve at high-K last process
A method for fabricating a semiconductor device includes providing a semiconductor substrate, forming on the semiconductor substrate a dummy gate interface...
US-9,502,402 Semiconductor device
A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end...
US-9,502,401 Integrated circuit with first and second switching devices, half bridge circuit and method of manufacturing
An integrated circuit includes a first switching device including a first semiconductor region in a first section of a semiconductor portion and a second...
US-9,502,400 Decoupling capacitor and method of making same
A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench...
US-9,502,399 Diode string circuit configurations with improved parasitic silicon-controlled rectifier (SCR) conduction...
Diode string configurations are provided that employ one or more guard bars (G.sub.BARS) positioned adjacent an end diode structure of a diode string to create...
US-9,502,398 Composite device with integrated diode
There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a...
US-9,502,397 3D interconnect component for fully molded packages
A method of making a semiconductor component package can include providing a substrate comprising conductive traces, soldering a surface mount device (SMD) to...
US-9,502,396 Air trench in packages incorporating hybrid bonding
A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second...
US-9,502,395 Power semiconductor package having vertically stacked driver IC
In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the...
US-9,502,394 Package on-Package (PoP) structure including stud bulbs and method
Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure...
US-9,502,393 Display device and method for manufacturing the same
Disclosed is a display device including features that suppresses threshold voltage variation among the oxide thin-film transistors of an array substrate and a...
US-9,502,392 Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects
A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface...
US-9,502,391 Semiconductor package, fabrication method therefor, and package-on package
Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The semiconductor package...
US-9,502,390 BVA interposer
A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation...
US-9,502,389 Display device using semiconductor light emitting device
Discussed is a display device including a wiring substrate having a first electrode and a second electrode formed on different surfaces, a conductive adhesive...
US-9,502,388 Switching element with a series-connected junction FET (JFET) and MOSFET achieving both improved withstand...
Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a...
US-9,502,387 Package-on-package structure with through molding via
Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the...
US-9,502,386 Fan-out package structure and methods for forming the same
A package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack...
US-9,502,385 Semiconductor device and connection checking method for semiconductor device
A package-on-package (POP), including a semiconductor device, and a multi-chip-package located above the semiconductor device, wherein the semiconductor device...
US-9,502,384 Semiconductor devices and semiconductor systems including the same
A semiconductor device may include a first input/output (I/O) unit and a second I/O unit. The first I/O unit may include a first input path that receives a...
US-9,502,383 3D integrated circuit package processing with panel type lid
Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.