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Semiconductor device comprising a slit insulating layer configured to pass
through a stacked structure
The semiconductor device may include a substrate including a trench. The semiconductor device may include an isolation layer formed in the trench and including...
Nonvolatile semiconductor memory device and method of manufacturing the
According to one embodiment, a memory device includes a first stacked layer structure stacked in order of a first insulating layer, a first electrode layer, . ....
Semiconductor integrated circuit device and a method of manufacturing the
A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first...
Set of stepped surfaces formation for a multilevel interconnect structure
A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench...
Sidewall assisted process for wide and narrow line formation
A method of forming narrow and wide lines includes forming mandrels separated by wider gaps and narrower gaps, forming sidewall spacers on sides of the gaps,...
Non-volatile memory device and method of manufacturing the same
A preliminary tunnel insulation pattern and a preliminary charge storage pattern are formed on each active pattern extending in a direction, and a trench is...
One time programming non-volatile memory cell
A one time programming non-volatile memory cell includes a first floating gate transistor with a single gate structure, an isolation transistor, and a select...
Semiconductor device and method of manufacturing the same
The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation...
Integrated circuit device featuring an antifuse and method of making same
One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region,...
Semiconductor device layout and method for forming the same
A semiconductor includes a gate line having a first portion in a transistor region and a second portion in a decoupling capacitor region.
Electromechanical nonvolatile memory
A semiconductor device includes an insulating layer on a semiconductor substrate, a bit line including TiAl and disposed on the insulating layer, a sidewall...
Semiconductor device and method for fabricating a semiconductor device
A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials...
Structure and method for highly strained germanium channel fins for high
A method is provided that includes providing a material stack of, from bottom to top, a relaxed and n-type doped silicon germanium alloy layer and a relaxed...
Structure for FinFETs
A FinFET device comprises a well over a substrate, an isolation region over the well and a fin line over the well and surrounded by the isolation region,...
Semiconductor devices with sidewall spacers of equal thickness
Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a...
Semiconductor device having a substrate including a first active region
and a second active region
A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active...
Semiconductor device including transistors having different threshold
A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a...
Method for providing an NMOS device and a PMOS device on a silicon
substrate and silicon substrate comprising...
The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS)...
Adjacent device isolation
An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a...
Semiconductor devices including raised source/drain stressors and methods
of manufacturing the same
A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a...
Semiconductor device structure with gate spacer having protruding bottom
portion and method for forming the same
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack...
Strained finFET device fabrication
A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a...
Semiconductor structure and manufacturing method thereof
The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a...
Multi-gate semiconductor devices
A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including...
FinFET device including fins having a smaller thickness in a channel
region, and a method of manufacturing same
A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate to a first thickness, forming a...
Integrating a planar field effect transistor (FET) with a vertical FET
One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a...
Semiconductor device and method of fabricating the same
Provided is a semiconductor device and method of fabricating the same. The device includes a substrate including a first region and a second region, a first...
Semiconductor device with authentication code
A plurality of contact trenches are formed in a semiconductor structure. The plurality of contact trenches are formed with a contact opening width selected to...
Epitaxial formation mechanisms of source and drain regions
The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown...
Method for core and in/out-put device reliability improve at high-K last
A method for fabricating a semiconductor device includes providing a semiconductor substrate, forming on the semiconductor substrate a dummy gate interface...
A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end...
Integrated circuit with first and second switching devices, half bridge
circuit and method of manufacturing
An integrated circuit includes a first switching device including a first semiconductor region in a first section of a semiconductor portion and a second...
Decoupling capacitor and method of making same
A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench...
Diode string circuit configurations with improved parasitic
silicon-controlled rectifier (SCR) conduction...
Diode string configurations are provided that employ one or more guard bars (G.sub.BARS) positioned adjacent an end diode structure of a diode string to create...
Composite device with integrated diode
There are disclosed herein various implementations of composite semiconductor devices. In one implementation, such a composite semiconductor device includes a...
3D interconnect component for fully molded packages
A method of making a semiconductor component package can include providing a substrate comprising conductive traces, soldering a surface mount device (SMD) to...
Air trench in packages incorporating hybrid bonding
A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second...
Power semiconductor package having vertically stacked driver IC
In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the...
Package on-Package (PoP) structure including stud bulbs and method
Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure...
Display device and method for manufacturing the same
Disclosed is a display device including features that suppresses threshold voltage variation among the oxide thin-film transistors of an array substrate and a...
Semiconductor device with embedded semiconductor die and
A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface...
Semiconductor package, fabrication method therefor, and package-on package
Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The semiconductor package...
A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation...
Display device using semiconductor light emitting device
Discussed is a display device including a wiring substrate having a first electrode and a second electrode formed on different surfaces, a conductive adhesive...
Switching element with a series-connected junction FET (JFET) and MOSFET
achieving both improved withstand...
Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a...
Package-on-package structure with through molding via
Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the...
Fan-out package structure and methods for forming the same
A package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack...
Semiconductor device and connection checking method for semiconductor
A package-on-package (POP), including a semiconductor device, and a multi-chip-package located above the semiconductor device, wherein the semiconductor device...
Semiconductor devices and semiconductor systems including the same
A semiconductor device may include a first input/output (I/O) unit and a second I/O unit. The first I/O unit may include a first input path that receives a...
3D integrated circuit package processing with panel type lid
Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the...