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Patent # Description
US-9,502,382 Coplaner waveguide transition
A coplanar waveguide transition includes a substrate, a first coplanar waveguide on a first side of the substrate, and a second coplanar waveguide on a second...
US-9,502,381 Semiconductor device, semiconductor package, and method for manufacturing semiconductor device
Embodiments of the present disclosure provide a semiconductor device, a semiconductor package, and a method for manufacturing a semiconductor device. The...
US-9,502,380 Three dimensional integrated circuits stacking approach
A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the method...
US-9,502,379 Super CMOS devices on a microelectronics system
A low cost IC solution is disclosed in accordance with an embodiment to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS...
US-9,502,378 Printed circuit boards having blind vias, method of testing electric current flowing through blind via thereof...
A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that...
US-9,502,377 Semiconductor package and fabrication method thereof
A semiconductor package is disclosed, which includes: a circuit board; a carrier disposed on the circuit board; an RF chip disposed on the carrier; a plurality...
US-9,502,376 Process for connecting joining parts
A method is provided for connecting parts to be joined. A first layer sequence is applied to a first part to be joined. The first layer sequence contains...
US-9,502,375 Semiconductor device with plated pillars and leads
A semiconductor device with plated pillars and leads is disclosed and may include a semiconductor die comprising a conductive pillar, a conductive lead...
US-9,502,374 Automatic wire tail adjustment system for wire bonders
A capillary is utilized to form the wedge wire bond comprised in a wire interconnection. A wire holding device is located above a wire clamp and the capillary...
US-9,502,373 Lid attach process and apparatus for fabrication of semiconductor packages
An adhesive dispenser comprises a dispensing head. The dispensing head comprises an adhesive material applicator portion on a first level of the dispensing...
US-9,502,372 Wafer-level packaging using wire bond wires in place of a redistribution layer
An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the...
US-9,502,371 Methods of forming wire interconnect structures
A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool;...
US-9,502,370 Semiconductor bonding structure and process
A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing...
US-9,502,369 Semiconductor devices and packages
Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a...
US-9,502,368 Picture frame stiffeners for microelectronic packages
A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An...
US-9,502,367 Semiconductor device including a cap facing a semiconductor chip and a bump electrode provided between the...
A semiconductor device according to an embodiment includes a semiconductor chip, a cap disposed to face the semiconductor chip, and having a through-hole...
US-9,502,366 Semiconductor structure with UBM layer and method of fabricating the same
A semiconductor structure with an under bump metallization (UBM) layer is provided. The semiconductor structure at least includes a substrate, a metal pad...
US-9,502,365 Opening in a multilayer polymeric dielectric layer without delamination
An integrated circuit and method with a delamination free opening formed through multiple levels of polymer dielectric. The opening has a vertical sidewall and...
US-9,502,364 Semiconductor package and method of forming the same
According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a backside redistribution layer; at least one...
US-9,502,363 Wafer level packages and methods for producing wafer level packages having delamination-resistant...
Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the...
US-9,502,361 Electronic device with stacked chips
An electronic device includes a first and a second integrated-circuit chip that are stacked at a distance from one another, and a plurality of electrical...
US-9,502,360 Stress compensation layer for 3D packaging
A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate...
US-9,502,359 Integrated circuit component shielding
Embodiments of shielding apparatuses are disclosed herein. In some embodiments, a shielding apparatus may include first and second conductive regions and a...
US-9,502,358 Integrated circuit having shielding structure
An integrated circuit includes a signal line and a plurality of shielding structures. The signal line is routed along a first direction and is in a first...
US-9,502,357 Alignment mark formation method and semiconductor device
According to one embodiment, at first, a first pattern is formed to an insulating film. Then, a first transparent film is formed on a region of the insulating...
US-9,502,356 Device and method with physical unclonable function
A physical unclonable function device, an encryptable electronic device, and a process for fabricating the physical unclonable function device are described. In...
US-9,502,355 Bottom package having routing paths connected to top package and method of manufacturing the same
A system, method, and computer program product are provided for producing a high bandwidth bottom package of a die-on-package structure. The method includes the...
US-9,502,354 Semiconductor device with layout of wiring layer and dummy patterns
A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The...
US-9,502,353 Semiconductor device having groove-shaped via-hole
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films...
US-9,502,352 Semiconductor wiring patterns
A semiconductor device includes a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal,...
US-9,502,351 Multiple split rail standard cell library architecture
A MOS device includes first and second sets of power rails. The first set of power rails extends across the MOS device and includes at least two power rails for...
US-9,502,350 Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer...
Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive...
US-9,502,349 Separated lower select line in 3D NAND architecture
Roughly described, a memory device has a multilevel stack of conductive layers which are divided laterally into separate word lines, each defining a block of...
US-9,502,348 Semiconductor device and fabrication method thereof
A method for forming a semiconductor device includes, sequentially, providing a substrate having a first region and a second region; forming a first dielectric...
US-9,502,347 Microelectronic assemblies formed using metal silicide, and methods of fabrication
Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and...
US-9,502,346 Integrated circuit with a sidewall layer and an ultra-thick metal layer and method of making
An integrated circuit that includes a substrate, a metal layer over the substrate and a first dielectric layer over the metal layer. The first dielectric layer...
US-9,502,345 Ball-grid-array package, electronic system and method of manufacture
A multiple-chip-package (MCP) has multiple chip groups and multiple package terminal groups for electrical connections in the MCP. Semiconductor chips of the...
US-9,502,344 Wafer level packaging of electronic device
Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one...
US-9,502,343 Dummy metal with zigzagged edges
A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation...
US-9,502,342 Semiconductor package and method of fabricating the same
A method of fabricating a package-on-package (PoP) type of semiconductor package may include providing a lower package with a lower substrate, a lower...
US-9,502,341 Printed circuit board and semiconductor package using the same
Embodiments of the inventive aspect include a printed circuit board and a semiconductor package using the same. The semiconductor package includes a substrate...
US-9,502,340 Method for manufacturing wiring board
A method for manufacturing a wiring board according to the present invention includes the steps of preparing a supporting substrate having a product forming...
US-9,502,339 Resin-encapsulated semiconductor device and its manufacturing method
A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100)...
US-9,502,338 Semiconductor package with switch node integrated heat spreader
In one implementation, a semiconductor package includes a patterned conductive carrier including partially etched segments. The semiconductor package also...
US-9,502,337 Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof
Flip-chip on leadframe (FCOL) semiconductor packaging structure and fabrication method thereof are provided. A semiconductor chip with copper pillars formed...
US-9,502,336 Coreless substrate with passive device pads
Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with...
US-9,502,335 Package structure and method for fabricating the same
A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on...
US-9,502,334 Method of making a semiconductor device package with dummy gate
A semiconductor device package includes a first substrate, which has a lower substrate surface and an upper substrate surface. A conductive dummy gate structure...
US-9,502,333 Semiconductor device having conductive vias
A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the...
US-9,502,332 Nonvolatile memory device and a method for fabricating the same
A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array...
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