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Patent # Description
US-9,502,331 Electric power converter with a spring member
An electric power converter includes a semiconductor module, a cooling pipe, a pressing member and a supporting member. A pair of supporting wall portions is...
US-9,502,330 Coolant distribution structure for monolithic microwave integrated circuits (MMICs)
A coolant distribution structure for an MMIC having: an input/output layer with an input port for receiving a coolant for transmission to coolant channels in...
US-9,502,329 Semiconductor module cooler
A semiconductor module cooler supplies a cooling medium to a cooling medium jacket from outside to cool a plurality of semiconductor elements thermally...
US-9,502,328 Silicon-on-plastic semiconductor device and method of making the same
A semiconductor device that does not produce nonlinearities attributed to a high resistivity silicon handle interfaced with a dielectric region of a buried...
US-9,502,327 Semiconductor device and method for manufacturing the same
A semiconductor device includes: a semiconductor element having a solder region and a non-solder region on a first face; a first metal member disposed on the...
US-9,502,326 Semiconductor device
A semiconductor device includes a transistor, a package in which the transistor is molded, a first heatsink plate, and a second heatsink plate. The first...
US-9,502,325 Integrated circuit barrierless microfluidic channel
A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This...
US-9,502,324 Electronic device
An electronic device having a heat generating element and a housing is provided including a heat dissipation arrangement provided between the heat generating...
US-9,502,323 Method of forming encapsulated semiconductor device package
Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a...
US-9,502,322 Molding compound supported RDL for IC package
One of the embodiments for a package substrate discloses a molding compound having plurality of metal pillar with middle portion embedded therein; a top end of...
US-9,502,321 Thin film RDL for IC package
A package substrate comprising a thin film redistribution layer (RDL) with a plurality of metal pillar configured on chip side is disclosed to thin the...
US-9,502,320 Semiconductor device
A semiconductor device includes an insulating substrate including a metal plate, an insulating plate, and a circuit plate laminated sequentially in order; a...
US-9,502,319 Driver integrated circuit chip and display device having the same
A driver integrated circuit chip includes a plurality of monitoring bumps, a plurality of output bumps, a plurality of first inner wires electrically connected...
US-9,502,318 Polish apparatus, polish method, and method of manufacturing semiconductor device
A polish apparatus including a rotatable table configured to receive a polish pad having a polish surface; a polish head configured to hold a polish object and...
US-9,502,317 Method for manufacturing light emitting device
A method for manufacturing a light emitting device includes providing a wafer including a substrate, a light emitting structure layer and a plurality of...
US-9,502,316 Method and device for producing a plurality optoelectronic elements
A method for producing a plurality of optoelectronic components may include measuring at least one measurement parameter for a first optoelectronic component...
US-9,502,315 Electrical component testing in stacked semiconductor arrangement
A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical...
US-9,502,314 Method for manufacturing tested apparatus and method for manufacturing system including tested apparatus
Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor...
US-9,502,313 Polysilicon resistor formation in silicon-on-insulator replacement metal gate finFET processes
A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over...
US-9,502,312 Area efficient field effect device
A novel semiconductor transistor is presented. The semiconductor structure has a gate region forming a channel with repetitive patterns in the direction...
US-9,502,311 Plasma protection diode for a HEMT device
A silicon substrate having a III-V compound layer disposed thereon is provided. A diode is formed in the silicon substrate through an ion implantation process....
US-9,502,310 Integration method for a vertical nanowire transistor
The present invention discloses a method for integrating a vertical nanowire transistor and belongs to a field of field effect transistor logic device in a CMOS...
US-9,502,309 Forming CMOSFET structures with different contact liners
A method of making a semiconductor device includes forming a first trench contact over a first source/drain region of a first transistor; forming a second...
US-9,502,308 Methods for forming transistor devices with different source/drain contact liners and the resulting devices
A method includes forming first and second contact openings so as to expose first and second source/drain regions, respectively, of a semiconductor material. At...
US-9,502,307 Forming a semiconductor structure for reduced negative bias temperature instability
An approach to forming a semiconductor structure with improved negative bias temperature instability includes forming an interfacial layer on a semiconductor...
US-9,502,306 Pattern formation method that includes partially removing line and space pattern
The present invention provides a pattern formation method of forming a pattern on a substrate by partially removing a line and space pattern formed on the...
US-9,502,305 Method for manufacturing CMOS transistor
A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is...
US-9,502,304 Semiconductor device and driver circuit with drain and isolation structure interconnected through a diode...
Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a...
US-9,502,303 Method for manufacturing semiconductor device with a barrier layer having overhung portions
A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural...
US-9,502,302 Process for integrated circuit fabrication including a uniform depth tungsten recess technique
Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first...
US-9,502,301 Fabrication methods for multi-layer semiconductor structures
Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a...
US-9,502,300 MEMS device and fabrication method thereof
The present disclosure provides a method for forming micro-electro-mechanical-system (MEMS) devices. The method includes providing a plurality of wafers;...
US-9,502,299 Semiconductor memory
A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions...
US-9,502,298 Asymmetric cyclic deposition and etch process for epitaxial formation mechanisms of source and drain regions
The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described uses Cl.sub.2 as an etchant during the...
US-9,502,296 Preventing delamination and cracks in fabrication of group III-V devices
In an exemplary implementation, a method includes growing a III-Nitride body over a group IV substrate in a semiconductor wafer. The method includes forming at...
US-9,502,295 Protective film material for laser processing and wafer processing method using the protective film material
A protective film material for protecting a surface of a wafer during a laser processing treatment contains a water soluble poly-N-vinyl acetamide. The...
US-9,502,294 Method and system for wafer level singulation
A method of singulating a plurality of semiconductor dies includes providing a carrier substrate and joining a semiconductor substrate to the carrier substrate....
US-9,502,293 Self-aligned via process flow
A method includes forming a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines embedded in a...
US-9,502,292 Dual shallow trench isolation liner for preventing electrical shorts
A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide...
US-9,502,291 Semiconductor magnetic memory device and method for manufacturing the same
A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first...
US-9,502,290 Oxidation-free copper metallization process using in-situ baking
A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over...
US-9,502,289 Selective formation of metallic films on metallic surfaces
Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic...
US-9,502,288 Method of forming an interconnect structure
An interconnect structure is provided that has improved electromigration resistance as well as methods of forming such an interconnect structure. The...
US-9,502,287 Method of preventing pattern collapse
A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom...
US-9,502,286 Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices
One method disclosed includes, among other things, forming a structure comprised of an island of a first insulating material positioned between the gate...
US-9,502,285 Method of forming trenches
A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality...
US-9,502,284 Metal thin film resistor and process
An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated...
US-9,502,283 Electron-beam (E-beam) based semiconductor device features
Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to...
US-9,502,282 Method of semiconductor manufacture utilizing layer arrangement to improve autofocus
In a method of manufacturing a semiconductor device using high-NA ArF liquid immersion exposure of a photoresist, a layer arrangement is provided capable of...
US-9,502,281 AVD hardmask for damascene patterning
A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a...
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