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Patent # Description
US-9,502,129 Memory system and method of controlling nonvolatile memory
According to one embodiment, a controller executes first refreshing in a case where a first value of a first block is larger than a first threshold and less...
US-9,502,128 Storage devices and methods of operating storage devices
A method of operating a storage device may include receiving a read command and a read address, performing a read operation on selected memory cells...
US-9,502,127 System optimization in flash memories
Methods of determining distributions may include performing a number of hard reads, performing a number of background reads at a frequency based on the number...
US-9,502,126 Memory system and operating method thereof
A method of operating a semiconductor memory device includes applying a read voltage to a selected word line on which a program operation is performed; applying...
US-9,502,125 Concurrently reading first and second pages of memory cells having different page addresses
In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The...
US-9,502,124 Nonvolatile memory device and method controlling word line setup time based on difference in setup voltage levels
A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory...
US-9,502,123 Adaptive block parameters
Data programmed in a block using a first set of programming parameters is read and a number of memory cells having threshold voltages in an intermediate...
US-9,502,122 Systems, devices and methods for memory operations
Systems, devices and methods are provided for memory operations. An example system includes: a latch circuit shared by a plurality of memory blocks of a memory...
US-9,502,121 Method and apparatus for reducing erase time of memory by using partial pre-programming
Memory cells of a nonvolatile memory array are characterized by one of multiple threshold voltage ranges including at least an erased threshold voltage range...
US-9,502,120 Programming memory cells dependent upon distortion estimation
A method for data storage includes accepting data for storage in an array of memory cells, which are arranged in rows associated with respective word lines....
US-9,502,119 Distributed capacitive delay tracking boost-assist circuit
According to one general aspect, an apparatus may include a plurality of voltage boosted circuits. Each voltage boosted circuit may include a power gater...
US-9,502,118 NAND memory addressing
Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory...
US-9,502,117 Cell-level statistics collection for detection and decoding in flash memories
Methods and apparatus are provided for collecting cell-level statistics for detection and decoding in flash memories. Data from a flash memory device is...
US-9,502,116 Nonvolatile semiconductor memory apparatus
According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array...
US-9,502,115 Amplifier stage
An input signal is amplified into an output signal that is to be applied to an electrical load including a capacitive component. An amplifier stage includes a...
US-9,502,114 Non-volatile ternary content-addressable memory with bi-directional voltage divider control and multi-step search
A cell for a non-volatile ternary content-addressable (TCAM) memory is provided. The cell comprises a first variable resistive element, a first transistor and a...
US-9,502,113 Configurable non-volatile content addressable memory
A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET...
US-9,502,112 Semiconductor memory device
A semiconductor memory device capable of a high-accuracy data search is provided. Each of the memory cells can hold two bits of information and includes a first...
US-9,502,111 Weighted equal cost multipath routing
In some implementations, network traffic can be routed along equal cost paths based on weights assigned to each path. For example, weighted equal cost multipath...
US-9,502,110 Modular cell for a memory array, the modular cell including a memory circuit and a read circuit
A memory cell for use within a memory array includes a memory circuit and a read circuit. The memory circuit includes a non-volatile memory element (for...
US-9,502,109 Non-volatile semiconductor storage device
Provided is a non-volatile semiconductor memory device capable of reliably preventing a malfunction of a read transistor without increasing the number of bit...
US-9,502,108 Programming memory cells using a program pulse
Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.
US-9,502,107 Writing multiple levels in a phase change memory
Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally...
US-9,502,106 Semiconductor memory device and method of controlling semiconductor memory device
According to one embodiment, a semiconductor memory device includes a cell array including a plurality of memory cells, a reference circuit, a sense amplifier...
US-9,502,105 Resistive memory device, operating method thereof, and system having the same
A resistive memory device includes a memory cell array including a plurality of resistive memory cells, an address decoder suitable for decoding an address...
US-9,502,104 Multi-level cell (MLC) non-volatile memory data reading method and apparatus
Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one...
US-9,502,103 Semiconductor memory device
A semiconductor memory device according to an embodiment includes: a semiconductor substrate; and a memory cell array which is arranged above the semiconductor...
US-9,502,102 MLC OTP operation with diode behavior in ZnO RRAM devices for 3D memory
Providing for a memory cell capable of forming a one time programmable, multi-level cell two-terminal memory cell or a rewritable, two terminal memory cell is...
US-9,502,101 Two-part programming methods
A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be...
US-9,502,100 Methods of operating sense amplifier circuits
A method of maintaining a voltage level of a bit line of a sense amplifier circuit includes providing a power supply voltage at a power supply node, receiving...
US-9,502,099 Managing skew in data signals with multiple modes
A method for controlling a memory includes causing a data de-skewer to operate in a writing mode, at the data de-skewer, receiving a first signal, and skewing...
US-9,502,098 Method of operating a voltage regulator to reduce contention current
A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first...
US-9,502,096 Protocol for memory power-mode control
In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store...
US-9,502,095 Memory system
A memory system is disclosed, which relates to a technology for reducing current consumption needed to perform a refresh operation in a Dual In-line Memory...
US-9,502,094 Method for driving memory element
To provide a memory element which keeps a stored logic state even without supply of power. To increase an effect of reducing power consumption by facilitating...
US-9,502,093 Method of writing to a spin torque magnetic random access memory
A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample...
US-9,502,092 Unipolar-switching perpendicular MRAM and method for using same
MRAM devices that are switched by unipolar electron flow are described. Embodiments use arrays of cells that include a diode or transistor with a pMTJ. The...
US-9,502,091 Sensing circuit for resistive memory cells
A sensing system may include a sense amplifier, a sensing circuit configured to sense a current difference, a data cell selectively coupled to the sensing...
US-9,502,090 Memory device including a domain wall and ferromagnetic driver nanowire
A memory device comprising a ferromagnetic data nanowire, a ferromagnetic driver nanowire, read element and/or a spaced write element positioned about the data...
US-9,502,089 Short detection and inversion
In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with...
US-9,502,088 Constant sensing current for reading resistive memory
Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage...
US-9,502,087 Electrically gated three-terminal circuits and devices based on spin hall torque effects in magnetic...
3-terminal magnetic circuits and devices based on the spin-transfer torque (STT) effect via a combination of injection of spin-polarized electrons or charged...
US-9,502,086 Method and system for analyzing double data rate (DDR) random access memory (RAM) signals and displaying DDR...
A logic analyzer and method of logic analysis: detect via one or more probes a plurality of signals associated with a double data rate (DDR) random access...
US-9,502,085 Memory buffers and modules supporting dynamic point-to-point connections
A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive...
US-9,502,084 Semiconductor integrated circuit with data latch control
A semiconductor integrated circuit may include: a memory block partitioned into a first region and a second region; a data latch unit configured to latch data...
US-9,502,083 Output buffer circuit with low sub-threshold leakage current
A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in...
US-9,502,082 Power management in dual memory platforms
Methods, apparatuses, and systems may provide a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM. A switch,...
US-9,502,081 Internal voltage generating circuit for generating internal voltage according to temperature and process variation
An internal voltage generation circuit may include a temperature information generation unit configured to generate a temperature code having a code value...
US-9,502,080 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells are disposed in a matrix, each memory cell being...
US-9,502,079 Passive interface for an electronic memory device
A passive interface for connecting an electronic memory device to an exterior circuit is provided. The passive interface includes a signal connection point, a...
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