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Patent # Description
US-9,508,731 Pillar arrangement in NAND memory
Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the...
US-9,508,730 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate in which a cell region and contact regions located at both sides of the cell region are defined, a first source...
US-9,508,729 Structure and method for a SRAM circuit
The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory...
US-9,508,728 CMOS gate stack structures and processes
A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the...
US-9,508,727 Integrated circuit device and method of manufacturing the same
A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active...
US-9,508,726 Semiconductor device and method of fabricating the same
A semiconductor device includes a device isolation pattern on a substrate to define active patterns, a gate electrode crossing the active patterns, first and...
US-9,508,725 Trench to trench fin short mitigation
A semiconductor structure includes a replacement strap for a finFET fin that provides communication between a storage capacitor and the fin. The storage...
US-9,508,724 Strained channel dynamic random access memory devices
DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
US-9,508,723 Semiconductor device having buried gate and manufacturing method thereof
A dummy active region is formed in a region in which a gate contact for supplying operation power to the buried gate is formed, and a PN junction diode...
US-9,508,722 Semiconductor arrangment with capacitor
A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory...
US-9,508,721 Metal gate structure of a CMOS semiconductor device
A semiconductor device includes a substrate comprising an isolation region surrounding a P-active region and an N-active region. The semiconductor device also...
US-9,508,720 Low leakage FinFET
An illustrative finFET comprises first, second, and third pluralities of fins having gate structures and source and drain regions formed on the fins so that...
US-9,508,719 Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for...
A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure is provided. The FinFET device structure includes a...
US-9,508,718 FinFET contact structure and method for forming the same
A device comprises a substrate comprising a first portion and a second portion separated by an isolation region, a first gate structure over the first portion,...
US-9,508,717 Integrated circuit device and repair method thereof
The present disclosure provides integrated circuit (IC) devices and repair methods of the IC devices. An IC device includes a PMOS transistor including a...
US-9,508,716 Methods of manufacturing a semiconductor device
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing...
US-9,508,715 Semiconductor structure
The present invention provides a semiconductor structure including a substrate, having a recess disposed thereon. Two first protruding portions are disposed on...
US-9,508,714 Multi-gate FETs and methods for forming the same
A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top...
US-9,508,713 Densely spaced fins for semiconductor fin field effect transistors
A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial...
US-9,508,712 Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such...
A nanowire device is disclosed that includes first and second nanowires, a gate structure positioned around a portion of the first and second nanowires and a...
US-9,508,711 Semiconductor device with bipolar junction transistor cells
A semiconductor device includes a bipolar junction transistor cell including an emitter region which is at least partly formed between mesas of a semiconductor...
US-9,508,710 Semiconductor device
A technology capable of suppressing a fluctuation in voltage in a diode region is provided. A resistance value between the emitter electrode and the lower body...
US-9,508,709 Semiconductor device, light-emitting device, and electronic device
An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect...
US-9,508,708 Poly resistor for metal gate integrated circuits
An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in...
US-9,508,707 Quantum well-modulated bipolar junction transistor
A semiconductor device includes a quantum well-modulated bipolar junction transistor (QW-modulated BJT) having a base with an area for a modulatable quantum...
US-9,508,706 Semiconductor integrated circuit
An input signal having a high level or a low level is input to a pad. A first protection element includes a first transistor configured as an N-channel MOSFET...
US-9,508,705 Electronic part, electronic device, and manufacturing method
An electronic part includes: a substrate; a first electrode configured to extend through the substrate and have a first opening size; a second electrode...
US-9,508,704 Method of fabricating semiconductor package, semiconductor package formed thereby, and semiconductor device...
The method of fabricating a semiconductor package including preparing a semiconductor wafer having a first side and a second side, the second side facing the...
US-9,508,703 Stacked dies with wire bonds and method
Semiconductor dies are bonded to each other and electrically connected to each other. An encapsulant is utilized to protect the semiconductor dies and external...
US-9,508,702 3D device packaging using through-substrate posts
A method for 3D device packaging utilizes through-substrate metal posts to mechanically and electrically bond two or more dice. The first die includes a set of...
US-9,508,701 3D device packaging using through-substrate pillars
A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of...
US-9,508,700 Semiconductor device module with solder layer
The present invention relates to a semiconductor device used in power equipment. The semiconductor device includes: a base plate; an insulating substrate...
US-9,508,699 Semiconductor package and method for manufacturing the same
A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second...
US-9,508,698 Light emitting device
A light emitting device includes a substrate having a top surface, upper and lower metal layers, multiple LED chips, at least one Zener diode, multiple...
US-9,508,697 Semiconductor light emitting device and semiconductor light emitting device package including the same
There is provided a semiconductor light-emitting device which includes a light-emitting diode (LED) chip having a first plane on which first and second...
US-9,508,696 Laser marking in packages
A package includes a device die, a first plurality of redistribution lines underlying the device die, a second plurality of redistribution lines overlying the...
US-9,508,695 Method of manufacturing light emitting device
A method of manufacturing a light emitting device includes: disposing a group of electrically conductive members on a support substrate, the group of the...
US-9,508,694 Multi-layer conductive backplane for LED light sheet segments
Relatively small, electrically isolated segments of LED light sheets are fabricated having an anode terminal and a cathode terminal. The segments contain...
US-9,508,693 Semiconductor device with heat sinks
An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more...
US-9,508,692 Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and...
A package can include a first, second and third semiconductor devices stacked in a first direction. A first semiconductor device can include a first through via...
US-9,508,691 Flipped die stacks with multiple rows of leadframe interconnects
Stacked microelectronic packages comprise microelectronic elements each having a contact-bearing front surface and edge surfaces extending away therefrom, and a...
US-9,508,690 Semiconductor TSV device package for circuit board connection
An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor...
US-9,508,689 Electrical connector between die pad and z-interconnect for stacked die assemblies
Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and...
US-9,508,688 Semiconductor packages with interposers and methods of manufacturing the same
A semiconductor package may include a first semiconductor chip, a second semiconductor chip disposed to overlap with a portion of the first semiconductor chip...
US-9,508,687 Low cost hybrid high density package
A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts...
US-9,508,686 Semiconductor device assembly with package interconnect extending into overlying spacer material, and...
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material...
US-9,508,685 Vertically integrated wafers with thermal dissipation
Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some...
US-9,508,684 Resin-encapsulated semiconductor device and method of manufacturing the same
A first resin encapsulated body (25) and a second resin encapsulated body (26) are stacked to form a resin-encapsulated semiconductor device. The first resin...
US-9,508,683 Semiconductor packages and methods for manufacturing the same
A semiconductor package and a method for manufacturing the same are provided. The semiconductor package may include a package substrate and at least one chip...
US-9,508,682 Organic EL luminescent device
An organic EL luminescent device (1) includes: organic EL panels of no smaller than 2 (10, 11) including a light-transmitting organic EL panel (10, 11), the...
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