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Patent # Description
US-9,508,681 Stacked semiconductor chip RGBZ sensor
An apparatus is described that includes a first semiconductor chip having a first pixel array. The first pixel array has visible light sensitive pixels. The...
US-9,508,680 Induction heating for underfill removal and chip rework
Underfill materials and methods for removing an underfill material from beneath a chip in relation to removal of the chip from a substrate. The underfill...
US-9,508,679 Mounting method
A mounting method of mounting chips on a substrate includes a temporarily-bonding process, and a main-bonding process. Temporarily-bonding process is to perform...
US-9,508,678 Method of manufacturing a semiconductor device including applying ultrasonic waves to a ball portion of the...
A method of manufacturing a semiconductor device which improves the reliability of a semiconductor device. The method of manufacturing the semiconductor device...
US-9,508,677 Chip package assembly and manufacturing method thereof
In one embodiment, a chip package assembly can include: a first substrate at a bottom layer, the first substrate having a first surface and a second surface...
US-9,508,676 Semiconductor package structure having hollow chamber and bottom substrate and package process thereof
A semiconductor package structure having hollow chamber includes a bottom substrate having a bottom baseboard and a bottom metal layer formed on a disposing...
US-9,508,675 Microelectronic package having direct contact heat spreader and method of manufacturing same
A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader...
US-9,508,674 Warpage control of semiconductor die package
Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the...
US-9,508,673 Wire bonding method
A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least...
US-9,508,672 Semiconductor device
A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21...
US-9,508,671 Semiconductor device and semiconductor package
The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element...
US-9,508,670 Semiconductor device including semiconductor chips stacked via relay substrate
A semiconductor device includes a support body provided with a wiring layer that includes a first pad; a first semiconductor chip; a first relay substrate...
US-9,508,669 Semiconductor device
A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically...
US-9,508,668 Conductive contacts having varying widths and method of manufacturing same
A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation...
US-9,508,667 Formation of solder and copper interconnect structures and associated techniques and configurations
Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations....
US-9,508,666 Packaging structures and methods with a metal pillar
A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over...
US-9,508,665 Method for insertion bonding and device thus obtained
A method for insertion bonding and a device thus obtained are disclosed. In one aspect, the device includes a first substrate having a front main surface and at...
US-9,508,664 Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive...
US-9,508,663 Assembly and packaging of MEMS device
A Micro Electro Mechanical systems (MEMS) device includes a solder bump on a substrate, a CMOS-MEMS die comprising a CMOS die and a MEMS die, and stud bumps on...
US-9,508,662 Optical semiconductor device
A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. In a cross-section...
US-9,508,661 Moisture barrier for semiconductor structures with stress relief
A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier...
US-9,508,660 Microelectronic die having chamfered corners
A microelectronic die may be formed with chamfer corners for reducing stresses which can lead to delamination and/or cracking failures when such a...
US-9,508,659 Method and apparatus to protect a wafer edge
A method includes holding bonded wafers by a wafer holding module. A gap between the bonded wafers along an edge is filled with a protection material.
US-9,508,658 Electromagnetic wall in millimeter-wave cavity
An apparatus having a package, a wall and a lid is disclosed. The package may be configured to mount a plurality of chips. Two of the chips may generate a...
US-9,508,657 Semiconductor package
A semiconductor device is provided. The semiconductor includes a semiconductor chip, a package substrate, and an electromagnetic interference (EMI) shielding...
US-9,508,656 Package structure and method for fabricating the same
A package structure includes a carrier, an electronic component disposed on the carrier, an encapsulant formed on the carrier for encapsulating the electronic...
US-9,508,655 Method for forming identification marks on refractory material single crystal substrate, and refractory...
An identification mark formation method for forming an identification mark on a refractory material single crystal substrate that is made of one selected from...
US-9,508,654 Method of manufacturing semiconductor device and structure including passivation film with a trench having...
A method of manufacturing a semiconductor device is provided. The method includes forming a passivation film on a substrate including a plurality of element...
US-9,508,653 Die-tracing in integrated circuit manufacturing and packaging
A method includes recording a wafer ID and a location ID of a device die in a database, and bonding the device die over a package substrate, wherein the device...
US-9,508,652 Direct IC-to-package wafer level packaging with integrated thermal heat spreaders
A method for wafer level packaging includes forming one or more die, forming a plated metal ring (PMR) on each die, forming a cover wafer (CW), the CW having...
US-9,508,651 Semiconductor device and method of manufacturing the same
A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump...
US-9,508,650 Semiconductor device with layout of wiring layer and dummy patterns
A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The...
US-9,508,649 Semiconductor devices
Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are...
US-9,508,648 Three-dimensional integrated circuit laminate, and interlayer filler for three-dimensional integrated circuit...
To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear...
US-9,508,647 Single damascene interconnect structure
A single damascene interconnect structure which includes a first layer that includes a first dielectric material having a first filled opening that has a...
US-9,508,646 Semicondutor device with copper plugs having different resistance values
Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one...
US-9,508,645 Contact pad structure
A contact pad structure includes alternately stacked N insulating layers (N.gtoreq.6) and N conductive layers, and has N regions arranged in a 2D array exposing...
US-9,508,644 Method of forming a pattern
A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask...
US-9,508,643 Electronic component
An electronic component includes: a plate-shaped semiconductor element connected to a metallic contacting by a sinter layer; a dielectric layer having a surface...
US-9,508,642 Self-aligned back end of line cut
Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal...
US-9,508,641 Semiconductor device and a method increasing a resistance value of an electric fuse
A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions...
US-9,508,640 Multiple via structure and method
A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric...
US-9,508,639 Package-in-substrate, semiconductor device and module
A package-in-substrate includes an exposed pad having a surface that is capable of contacting the outside; a semiconductor chip arranged on a surface opposite...
US-9,508,638 Making electrical components in handle wafers of integrated circuit packages
A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first...
US-9,508,637 Protrusion bump pads for bond-on-trace processing
An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The...
US-9,508,636 Integrated circuit package substrate
Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment...
US-9,508,635 Methods of forming conductive jumper traces
Methods of forming conductive jumper traces for semiconductor devices and packages. Substrate is provided having first, second and third trace lines formed...
US-9,508,634 Package structure
A package structure includes a lead frame, a selective-electroplating epoxy compound, conductive vias and a patterned circuit layer. The lead frame includes a...
US-9,508,633 High performance power transistor having ultra-thin package
A field-effect transistor package includes a leadframe with a first linear thickness (150a) and a leadframe pad (151) of a reduced thickness; a first terminal...
US-9,508,632 Apparatus and methods for stackable packaging
A semiconductor structure includes a lead frame having a flag and a plurality of leads, a semiconductor die attached to a first major surface of the flag, and a...
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