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Patent # Description
US-9,515,179 Electronic devices including a III-V transistor having a homostructure and a process of forming the same
An electronic device can include a vertical III-V transistor having a gate electrode and a channel region within a homostructure. The channel region can be...
US-9,515,178 Shielded trench semiconductor devices and related fabrication methods
Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device includes gate structures within a semiconductor...
US-9,515,177 Vertically integrated semiconductor device and manufacturing method
A vertically integrated semiconductor device in accordance with various embodiments may include: a first semiconducting layer; a second semiconducting layer...
US-9,515,176 Silicon carbide bipolar junction transistor including shielding regions
A silicon carbide (SiC) bipolar junction transistor (BJT) and a method of manufacturing such a SiC BJT is provided. The SiC BJT can include a collector region...
US-9,515,175 Semiconductor device and method for manufacturing the same
A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. In a semiconductor device including a bottom-gate...
US-9,515,174 Method of manufacturing a semiconductor storage device
A method for manufacturing a semiconductor storage device includes forming a first insulating film on a semiconductor substrate; forming a first conductive...
US-9,515,173 Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors
Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The...
US-9,515,172 Semiconductor devices having isolation insulating layers and methods of manufacturing the same
The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin...
US-9,515,171 Radiation tolerant device structure
Techniques for producing radiation tolerant device structures are provided. In one aspect, a method for forming a radiation-hardened device includes the steps...
US-9,515,170 Semiconductor device and method for manufacturing the same
An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a...
US-9,515,169 FinFET and method of manufacturing same
There is provided a FinFET fabricating method, comprising: a. providing a substrate ; b. forming a fin on the substrate; c. forming a channel protective layer...
US-9,515,168 Fin end spacer for preventing merger of raised active regions
After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a...
US-9,515,167 Raised epitaxial LDD in MuGFETs and methods for forming the same
Embodiments include Multiple Gate Field-Effect Transistors (MuGFETs) and methods of forming them. In an embodiment, a structure includes a substrate, a fin,...
US-9,515,166 Selective atomic layer deposition process utilizing patterned self assembled monolayers for 3D structure...
Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three...
US-9,515,165 III-V field effect transistor (FET) with reduced short channel leakage, integrated circuit (IC) chip and method...
Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a...
US-9,515,164 Methods and structure to form high K metal gate stack with single work-function metal
A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes...
US-9,515,163 Methods of forming FinFET semiconductor devices with self-aligned contact elements using a replacement gate...
One method disclosed herein includes removing a sacrificial gate structure and forming a replacement gate structure in its place, after forming the replacement...
US-9,515,162 Surface treatment of semiconductor substrate using free radical state fluorine particles
A substrate having a buffer layer and a barrier layer is formed. The buffer and barrier layers have different bandgaps such that an electrically conductive...
US-9,515,161 Monolithically integrated self-aligned GaN-HEMTs and schottky diodes and method of fabricating the same
Monolithic integration of high-frequency GaN-HEMTs and GaN-Schottky diodes. The integrated HEMTs/Schottky diodes are realized using an epitaxial structure and a...
US-9,515,160 Silicon carbide semiconductor device and method for producing the same
In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion...
US-9,515,159 Electronic sensor apparatus for detecting chemical or biological species, microfluidic apparatus comprising...
An electronic sensor apparatus for detecting chemical or biological species includes a semiconductor chip, a sensor device, and a substrate. The chip is...
US-9,515,158 Semiconductor structure with insertion layer and method for manufacturing the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the...
US-9,515,157 Sensor arrangement comprising a carrier substrate and a ferroelectric layer and method for producing and using...
A sensor arrangement comprises a carrier substrate and a ferroelectric layer disposed on the carrier substrate, wherein the sensor arrangement comprises means...
US-9,515,156 Air gap spacer integration for improved fin device performance
A method for providing a FinFET device with an air gap spacer includes providing a substrate a plurality of fins and a dummy gate arranged transverse to the...
US-9,515,155 E-fuse design for high-K metal-gate technology
E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed...
US-9,515,154 Thin film transistor, display apparatus comprising the same, method of manufacturing thin film transistor, and...
A thin film transistor includes a polysilicon layer on a substrate, which includes a first area between second and third areas. A polysilicon layer is formed on...
US-9,515,153 Semiconductor device and method for manufacturing the same
A semiconductor device with enhanced reliability in which a gate electrode for a trench-gate field effect transistor is formed through a gate insulating film in...
US-9,515,152 Simple and cost-free MTP structure
Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate....
US-9,515,151 Gettering agents in memory charge storage structures
Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing...
US-9,515,150 Semiconductor devices and methods of manufacturing the same
Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second...
US-9,515,149 Power semiconductor device
A semiconductor device includes an active region and a semiconductor substrate layer having a lower part semiconductor layer of a second conductivity type. The...
US-9,515,148 Bridging local semiconductor interconnects
A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS...
US-9,515,147 Semiconductor device including nanowire transistor
A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel...
US-9,515,146 Nitride semiconductor layer, nitride semiconductor device, and method for manufacturing nitride semiconductor layer
According to one embodiment, a nitride semiconductor layer spreading along a first surface is provided. The nitride semiconductor layer includes a first region...
US-9,515,145 Vertical MOSFET device with steady on-resistance
A semiconductor device capable of reducing ON-resistance changes with temperature, including a semiconductor substrate of a first conductivity type, a drift...
US-9,515,144 Fin-type graphene device
Example embodiments relate to a fin-type graphene device. The fin-type graphene device includes a substrate, a graphene channel layer substantially vertical to...
US-9,515,143 Heterogeneous layered structure, method of preparing the heterogeneous layered structure, and electronic device...
A method of manufacturing a heterogeneous layered structure includes growing a hexagonal boron nitride sheet directly on a metal substrate in a chamber,...
US-9,515,142 Active regions with compatible dielectric layers
A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure...
US-9,515,141 FinFET device with channel strain
A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate,...
US-9,515,140 Patterned strained semiconductor substrate and device
A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and...
US-9,515,139 Trap rich layer formation techniques for semiconductor devices
A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some...
US-9,515,138 Structure and method to minimize junction capacitance in nano sheets
A method of making a semiconductor device includes forming a nanosheet stack including a first layer and a second layer; patterning a gate stack on the...
US-9,515,137 Super junction semiconductor device with a nominal breakdown voltage in a cell area
A super junction semiconductor device includes a super junction structure that is formed in a semiconductor body having a first and a second, parallel surface....
US-9,515,136 Edge termination structure for a power integrated device and corresponding manufacturing process
An integrated device has: a structural layer of semiconductor material doped with a first conductivity type and having a top surface defining a plane; a...
US-9,515,135 Edge termination structures for silicon carbide devices
An edge termination structure for a silicon carbide semiconductor device includes a plurality of spaced apart concentric floating guard rings in a silicon...
US-9,515,133 Inductor device and fabrication method
A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes an inductor disposed on a surface...
US-9,515,132 Organic electroluminescent display device and method of manufacturing the same
A substrate on which a plurality of pixel electrodes are disposed is prepared. An organic electroluminescent film 22 is formed with the inclusion of a common...
US-9,515,131 Narrow border organic light-emitting diode display
An electronic device may be provided having an organic light-emitting diode display and control circuitry for operating the display. The display may include one...
US-9,515,130 Covering method and organic EL element manufacturing method
A covering method including: preparing a mixture containing insulative material and a solvent; applying the mixture over a defective portion; and covering the...
US-9,515,129 Organic light emitting display apparatus and manufacturing method thereof
An organic light emitting display apparatus includes pixel areas, each pixel area having emission and non-emission areas; a first electrode corresponding to the...
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