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Patent # Description
US-9,515,028 Array substrate, method of manufacturing the same and display device
An array substrate and manufacturing method thereof, and a display device are provided. The array substrate comprises a TFT, an isolating layer (M), a pixel...
US-9,515,027 Printed circuit board
A printed circuit board includes a printed circuit board, a semiconductor device mounted on the printed circuit board, a capacitor element mounted on the...
US-9,515,026 Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices...
A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark...
US-9,515,025 Stretchable form of single crystal silicon for high performance electronics on rubber substrates
The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when...
US-9,515,024 Structures with through vias passing through a substrate comprising a planar insulating layer between semiconductor
A through via contains a conductor (244, 262) passing through a substrate (140). The substrate can be SOI or some other substrate containing two semiconductor...
US-9,515,023 Multilevel contact to a 3D memory array and method of making thereof
A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of...
US-9,515,022 Semiconductor device with air gap and method for fabricating the same
A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a...
US-9,515,021 Semiconductor structure and method of forming the same
A semiconductor device with metal-doped etch stop layer therein and a method of manufacturing the same is disclosed. The method includes forming an...
US-9,515,020 Semiconductor device and method of manufacturing the same
A semiconductor device includes a plurality of transistors formed over a substrate, a support body including a horizontal portion and protrusions, wherein the...
US-9,515,019 Semiconductor device
The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is...
US-9,515,018 Wiring substrate and method for manufacturing wiring substrate
A wiring substrate includes an insulating layer, a wiring layer, a via wiring, and a solder resist layer. The wiring layer includes a pad body that constitutes...
US-9,515,017 Ground via clustering for crosstalk mitigation
Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated...
US-9,515,016 Semiconductor package and method of forming z-direction conductive posts embedded in structurally protective...
A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over...
US-9,515,015 Housing for an electronic component, an electronic assembly, method of producing a housing for an electronic...
A housing includes a lead frame formed from electrically conductive material having first and second sides, a contact section contacting an electronic component...
US-9,515,014 Power converter package with integrated output inductor
In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also...
US-9,515,013 Semiconductor device
A semiconductor device includes a package part having a semiconductor element sealed in resin, a plurality of first leads each having an outer portion extending...
US-9,515,012 Package of power dies and three-phase power converter
The present invention concerns a package of power dies composed of a first part and a second part, the first part including a plaque having cavities on which...
US-9,515,011 Over-mold plastic packaged wide band-gap power transistors and MMICS
A transistor package includes a lead frame, a wide band-gap transistor attached to the lead frame, and an over-mold surrounding the lead frame and the wide...
US-9,515,010 Semiconductor packaging structure and forming method therefor
The present invention provides a semiconductor package structure, including: a chip, wherein bonding pads and a passivation layer are arranged on the surface of...
US-9,515,009 Packaged semiconductor device having leadframe features preventing delamination
A semiconductor device has a leadframe with a first (401a) and a parallel second surface, and an assembly pad (410) bordered by two opposing sides, which...
US-9,515,008 Techniques for interconnecting stacked dies using connection sites
An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof....
US-9,515,007 Substrate structure
A substrate structure includes: a substrate body defined with a layout area, a sealing member and a cutting area, the sealing member being adjacent to the...
US-9,515,006 3D device packaging using through-substrate posts
A method for 3D device packaging utilizes through-hole metal post techniques to mechanically and electrically bond two or more dice. The first die includes a...
US-9,515,005 Package mounting structure
A package mounting structure includes: a first substrate having wiring; a second substrate having wiring; at least one cooling unit having a first face and a...
US-9,515,004 Thermal interface materials
A thermal interface material is configured for use with an electronic device for transferring heat between heat generating components and heat removing...
US-9,515,003 Embedded air core inductors for integrated circuit package substrates with thermal conductor
Embedded air core inductors are described for integrated circuit package substrates. The substrates have a thermal conductor for the inductors. One example...
US-9,515,002 Bonding pads with thermal pathways
Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal...
US-9,515,001 Semiconductor device having potential monitoring terminal to monitor potential of power-supply line
Disclosed herein is a device that includes an internal circuit, a first terminal supplied with a first voltage, a first power-supply line coupled between the...
US-9,515,000 Method for manufacturing semiconductor device
The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the...
US-9,514,999 Systems and methods for semiconductor line scribe line centering
Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a...
US-9,514,998 Polysilicon resistor formation in silicon-on-insulator replacement metal gate finFET processes
A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over...
US-9,514,997 Silicon-germanium FinFET device with controlled junction
Embodiments of the invention include a method for forming a FinFET device and the resulting structure. A semiconductor device including a substrate, a...
US-9,514,996 Process for fabricating SOI transistors for an increased integration density
A process for fabricating field-effect transistors, including providing a first semiconductor band surmounted with a first semiconductor layer; providing a...
US-9,514,995 Implant-free punch through doping layer formation for bulk FinFET structures
A punch through stop layer is formed in a bulk FinFET structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by...
US-9,514,994 FinFET device and fabrication method thereof
A method for forming a FinFET device is provided. The method includes providing a substrate having a first region and a second region; and forming a plurality...
US-9,514,993 Method for manufacturing semiconductor devices comprising epitaxial layers
A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed...
US-9,514,992 Unidirectional spacer in trench silicide
A semiconductor device includes a trench region in an interconnect level dielectric layer. A silicide layer is on the bottom of the trench region. Opposing...
US-9,514,991 Method of manufacturing a FinFET device having a stepped profile
A FinFET device and a method for fabricating a FinFET device are disclosed. An exemplary method of fabricating a FINFET device includes providing a substrate...
US-9,514,990 Methods for manufacturing semiconductor devices having different threshold voltages
Methods for manufacturing a semiconductor device including a field effect transistor include forming first fins protruding from a substrate including a first...
US-9,514,989 Guard rings including semiconductor fins and regrown region
A method includes forming a semiconductor fin, which forms a ring, forming a plurality of gate stacks on sidewalls and a top surface of each of sides of the...
US-9,514,988 Semiconductor devices and packaging methods thereof
Packaged semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a method of packaging semiconductor devices comprises...
US-9,514,987 Backside contact to final substrate
Device structures and fabrication methods for a backside contact to a final substrate An electrically-conducting connection is formed that extends through a...
US-9,514,986 Device with capped through-substrate via structure
A device including a first dielectric layer on a semiconductor substrate, a gate electrode formed in the first dielectric layer, and a through-substrate via...
US-9,514,985 Electroless metal through silicon via
A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface,...
US-9,514,984 Semiconductor device and method for manufacturing same
A method for manufacturing a semiconductor device includes forming an insulating layer on a semiconductor layer; forming a metal layer on the insulating layer;...
US-9,514,983 Cobalt based interconnects and methods of fabrication thereof
A metal interconnect comprising cobalt and method of forming a metal interconnect comprising cobalt are described. In an embodiment, a metal interconnect...
US-9,514,982 Semiconductor structure and manufacturing method of the same
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate having a trench, a stacked strip...
US-9,514,981 Interconnect structure
An interconnect structure includes a dielectric layer with one or more trenches extending therein, one or more interconnect lines, and one or more first liner...
US-9,514,980 Semiconductor device with air gap and method for fabricating the same
A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming...
US-9,514,979 Trench formation using horn shaped spacer
A method includes forming a mandrel layer over a target layer, and etching the mandrel layer to form mandrels. The mandrels have top widths greater than...
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