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Patent # Description
US-9,514,827 Memory device, memory system and method of operating memory device
A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic...
US-9,514,826 Programming method for NAND-type flash memory
The invention provides a programming method for a NAND-type flash memory capable of reducing the drop in reliability due to data-rewriting. The programming...
US-9,514,825 Semiconductor storage device and controller
A semiconductor storage device includes memory cells, select transistors, memory strings, a block, word lines, and select gate lines. In the memory string, the...
US-9,514,824 Partial local self boosting for NAND
A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied...
US-9,514,823 Programming algorithm for improved flash memory endurance and retention
A method applies a first set of consecutive pulses to flash memory cells in one or more flash memory devices to program the flash memory cells using a first...
US-9,514,822 Flash memory device
A flash memory device is disclosed. The flash memory device includes: a cell array region; an X-decoder region arranged adjacent to the cell array region in a...
US-9,514,821 Discharge circuit
A discharge circuit includes a first circuit connected between a high-voltage terminal and a connection node, wherein first circuit includes a depletion high...
US-9,514,820 EEPROM architecture wherein each bit is formed by two serially connected cells
An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line....
US-9,514,819 Programming method, memory storage device and memory controlling circuit unit
A programming method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a first write command; and...
US-9,514,818 Memristor using parallel asymmetrical transistors having shared floating gate and diode
A two-terminal, single-poly floating gate memristor includes parallel-connected, asymmetrical readout and injection transistors having a shared floating gate...
US-9,514,817 Non-volatile memory device with memristor
A non-volatile memory device includes plural non-memory cells. Each non-volatile memory cell includes a first switch, a first memristor, a second switch, a...
US-9,514,816 Non-volatile static RAM and method of operation thereof
A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM)...
US-9,514,815 Verify scheme for ReRAM
Circuitry coupled to a programmable element comprising metal oxide is configured to execute a program-verify operation including: an initial cycle of a program...
US-9,514,814 Memory write driver, method and system
Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of...
US-9,514,813 Resistive memory device, resistive memory system, and operating method thereof
A method for operating a memory device includes sensing a temperature of the resistive memory device, setting a level of a set voltage or current for writing to...
US-9,514,812 Apparatus and method for reading a storage device with a ring oscillator and a time-to-digital circuit
According to an example, a method for storage device reading may include receiving an input signal indicative of a period of oscillation of a ring oscillator...
US-9,514,811 Access signal adjustment circuits and methods for memory cells in a cross-point array
Systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, are described. In at...
US-9,514,810 Resistive non-volatile memory cell and method for programming same
A memory has a word line, a bit line, a plurality of resistive non-volatile memory (RNVM) cells coupled to the word line, and a first source line and a second...
US-9,514,809 Memory array plane select
Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged...
US-9,514,807 Variable resistance memory device
A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper...
US-9,514,806 Auto low current programming method without verify
A flash memory device employs a low current auto-verification programming scheme using multi-step programming voltage and cell current detection. The low...
US-9,514,805 Intelligent bit line precharge for improved dynamic power
A method and apparatus for writing data to a memory device are provided that do not change the precharge states for a bit line pair in a current write cycle if...
US-9,514,804 Multi-state configuration RAM cell
A multi-state static RAM cell includes N NOR gates. Each NOR gate has N-1 inputs and one output. The output of each NOR gate is coupled to a different bit line....
US-9,514,803 Semiconductor memory having electrically floating body transistor
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to...
US-9,514,802 Volatile memory self-defresh
Embodiments of the inventive concept include a volatile memory device including a memory cell array, the memory cell array including multiple rows and/or banks...
US-9,514,801 Semiconductor device generating a refresh signal
A semiconductor device includes a temperature code latch circuit and a period selection circuit. The temperature code latch circuit latches a count code having...
US-9,514,800 DRAM and self-refresh method
A dynamic random access memory (DRAM) with code bit and self-refresh operation is disclosed. In one particular exemplary embodiment, at least one code bit is...
US-9,514,799 Memory scheduling method and memory controller
In a memory scheduling method, a memory controller writes a first group of first row strobe commands (ACTs) into a first memory. The first group of first ACTs...
US-9,514,798 Address storage circuit and memory and memory system including the same
A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address...
US-9,514,797 Hybrid reference generation for ferroelectric random access memory
An apparatus that includes a reference generating circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference...
US-9,514,796 Magnetic storage cell memory with back hop-prevention
An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a...
US-9,514,795 Reverse complement magnetic tunnel junction (MTJ) bit cells employing shared source lines, and related methods
Reverse complement MTJ bit cells employing shared source lines are disclosed. In one aspect, a 2T2MTJ reverse complement bit cell employing shared source line...
US-9,514,794 Information processing apparatus, information processing system and phase adjusting method
An information processing apparatus configured to adjust a phase relation between a data signal and a strobe signal includes a processor and memory. The memory...
US-9,514,793 Semiconductor memory device and operating method thereof
A semiconductor memory device includes a plurality of data buffering units corresponding to a data line, wherein the data buffering units include a first data...
US-9,514,792 Semiconductor device having stacked layers
A semiconductor device is disclosed in which there are provided a first substrate including memory cells and at least one bit line electrically coupled to the...
US-9,514,791 Facilitating communication between memory devices of different technologies
According to one embodiment, an apparatus comprises one or more memory devices and one or more processors coupled to a circuit board. The memory devices are...
US-9,514,790 Data transmission circuit
A data transmission circuit may include data line groups and pass sections arranged among the data line groups to allow the data line groups to form one line....
US-9,514,789 Systems and methods for safely moving short term memory devices while preserving, protecting and examining...
The present invention provides a method for safely recovering, protecting, and reading short term memory devices, such as DRAM modules, following their...
US-9,514,788 Differential amplifier circuit, voltage regulator, and semiconductor memory device including the same
The present invention relates to a differential amplifier circuit. A differential amplifier circuit has an advantage in that it can improve a voltage drop...
US-9,514,787 Magnetic disk apparatus, read/write control method, and controller
According to at least one embodiment, a magnetic disk apparatus includes a magnetic disk, a nonvolatile memory, a determination module, a write module, and a...
US-9,514,786 Electronic device and music visualization method thereof
An electronic device and a music visualization method thereof are provided. The electronic device is configured to display music visualization in response to...
US-9,514,785 Providing content item manipulation actions on an upload web page of the content item
A system and method to provide content item manipulation actions for a content item on an upload web page is presented. The method can include initializing an...
US-9,514,784 Terminal and operating method thereof
A method of controlling a mobile terminal, and which includes obtaining, via a camera of the mobile terminal, an image of a user; playing a video on a display...
US-9,514,783 Video editing with connected high-resolution video camera and video cloud server
An apparatus having a server is disclosed. The server may be configured to (i) receive via a network a first clip of video generated by a camera, (ii) receive...
US-9,514,782 Method and system for activation of an optical article
A method for activating an optical article includes providing an optical article, wherein at least one mark is disposed on the optical article, wherein the mark...
US-9,514,781 Data storage component test deck system
A system may utilize at least an enclosed test deck that has an access port door covering an access port. The system can test a data storage component by...
US-9,514,780 Free fall detection system for protecting hard drives in mobile devices
In a method for detecting free fall, a first acceleration parallel to a first axis, a second acceleration parallel to a second axis perpendicular to the first...
US-9,514,779 Method for manufacturing multilayer structure sheet, and optical information recording medium
A method for manufacturing a multilayer structure sheet for manufacturing an optical information recording medium having a multilayer structure with a plurality...
US-9,514,778 Optical disc device and spherical aberration error signal detection method
There is provided an optical disc device that performs recording on a land and a groove, including an optical path splitter configured to split a luminous flux...
US-9,514,777 Servo processor receiving photodetector signals
An optical disk drive and a digital servo method for the optical disk drive includes controlling functions of the optical disk drive with a microprocessor....
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