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Patent # Description
US-9,514,072 Management of allocation for alias devices
An input/output (I/O) request is received that indicates a priority for performing the received I/O request by a storage controller. If a base device is not...
US-9,514,070 Debug control circuit
A method and apparatus store a command in a command register and set, with a control circuit, a first operation mode associated with a split transaction for...
US-9,514,069 Enhanced computer processor and memory management architecture
Disclosed in some examples is an improved computing architecture, which includes multiple processor cores and I/O devices communicating with multiple memory...
US-9,514,068 Broadcast and unicast communication between non-coherent processors using coherent address operations
Non-address data is received that is to be transmitted on a non-transitory communication medium communicably coupling a plurality of devices, wherein the...
US-9,514,067 Interface arbitration for a wired tag
Various exemplary embodiments relate to an integrated circuit (IC) including: a memory; a radio frequency (RF) interface configured to access the memory; a...
US-9,514,066 Reconfigurable interface and method of configuring a reconfigurable interface
A real-time reconfigurable input/output interface of a controller and a method of reconfiguring the same. The reconfigurable interface enables the controller to...
US-9,514,065 Host device coupled to a USB peripheral and method of operating the same
Embodiments of the present invention relate to methods and apparatus for operating a host device (e.g. a `plug-and-play` host device) coupled to a peripheral...
US-9,514,064 Protection scheme for embedded code
A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes...
US-9,514,063 Secure compact flash
Methods and apparatus are provided, such as a memory card with a processor and nonvolatile memory coupled thereto. The nonvolatile memory has a secure area...
US-9,514,062 Storage method for a gaming machine
In a first aspect the invention provides a storage method for a gaming machine, including allocating program code to one of at least two program categories...
US-9,514,061 Method and apparatus for cache tag compression
A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored...
US-9,514,060 Device, system and method of accessing data stored in a memory
Device, system and method of accessing data stored in a memory. For example, a device may include a memory to store a plurality of data items to be accessed by...
US-9,514,059 Hiding page translation miss latency in program memory controller by selective page miss translation prefetch
This invention hides the page miss translation latency for program fetches. In this invention whenever an access is requested by CPU, the L1I cache controller...
US-9,514,058 Local page translation and permissions storage for the page window in program memory controller
This invention provides a current page translation register storing virtual to physical address translation data for a single current page and optionally access...
US-9,514,057 Storage module and method for managing logical-to-physical address mapping
A storage module and method for managing logical-to-physical address mapping are disclosed. In one embodiment, a storage module is provided comprising a memory...
US-9,514,056 Virtual memory system, virtual memory controlling method, and program
Disclosed herein is a virtual memory system including a nonvolatile memory allowing random access, having an upper limit to a number of times of rewriting, and...
US-9,514,055 Distributed media cache for data storage systems
This disclosure is related to distributed media cache for data storage systems, such as disc drives, flash devices, or hybrid devices. In one example, a data...
US-9,514,054 Method to persistent invalidation to ensure cache durability
A method and system of persistent cache invalidation ensures cache durability. A storage filter driver of a storage input/output (I/O) stack of a server may be...
US-9,514,053 Providing memory system programming interfacing
A memory system implements a plurality of cache eviction policies, a plurality of virtual address modification policies, or both. One or more application...
US-9,514,052 Write-through-and-back-cache
Embodiments are provided for cache memory systems. In one general embodiment, a method that includes receiving a host write request from a host computer,...
US-9,514,051 Cache memory with unified tag and sliced data
A cache memory is shared by N cores of a processor. The cache memory includes a unified tag part and a sliced data part partitioned into N data slices. Each...
US-9,514,050 Caching in multicore and multiprocessor architectures
A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at...
US-9,514,049 Cache backing store for transactional memory
In response to a transactional store request, the higher level cache transmits, to the lower level cache, a backup copy of an unaltered target cache line in...
US-9,514,048 Inducing transactional aborts in other processing threads
In a transactional memory environment, a computer-implemented method includes a first processor initiating a first transaction and encountering an abort...
US-9,514,047 Apparatus and method to dynamically expand associativity of a cache memory
In an embodiment, a processor includes at least one core, a cache memory, and a cache controller. Responsive to a request to store an address of a data entry...
US-9,514,046 Dynamic detection and software correction of incorrect lock and atomic update hint bits
A hint bit detection and correction method uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions...
US-9,514,045 Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
A technique for operating a cache memory of a data processing system includes creating respective pollution vectors to track which of multiple concurrent...
US-9,514,044 Multi-level cache tracking table
Disclosed herein are a computing system, integrated circuit, and method to enhance retrieval of cached data. A tracking table is used to initiate a search for...
US-9,514,043 Systems and methods for utilizing wear leveling windows with non-volatile memory systems
Systems and methods for utilizing wear leveling windows with non-volatile memory systems are disclosed. In one implementation, a memory management module of a...
US-9,514,042 Method for managing memory apparatus to perform writing control according to monitored data amount of received...
A method for managing a memory apparatus and the associated memory apparatus thereof and the associated controller thereof are provided, where the method...
US-9,514,041 Memory controller and memory system
A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the...
US-9,514,040 Memory storage device and memory controller and access method thereof
A memory storage device and a memory controller and an access method thereof are provided. The memory storage device includes a rewritable non-volatile memory...
US-9,514,039 Determining a metric considering unallocated virtual storage space and remaining physical storage space to use...
Provided are a method, system, and computer program product for determining a metric to use to determine whether to generate a low space alert. A determination...
US-9,514,038 Managing memory systems containing components with asymmetric characteristics
A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a...
US-9,514,037 Test program scheduling based on analysis of test data sets
A computer program product includes a tangible storage medium storing instructions for execution by a processing circuit for performing a method. The method...
US-9,514,036 Test case generation
Embodiments of the present invention provide methods, computer program products, and systems for generating comprehensive test cases covering new events yet to...
US-9,514,035 Coverage driven generation of constrained random stimuli
A method, system and computer readable medium for coverage driven generation of stimuli for DUT verification. The method may include receiving, via an input...
US-9,514,034 Ordered test execution to enable faster feedback
Methods, systems, and computer-readable media for ordered test execution to enable faster feedback are disclosed. A likelihood of failure is estimated for...
US-9,514,033 Systems and methods for processing software application metadata associated with a software application
Systems and methods for processing software application metadata associated with a software application are provided. A representative method includes the step...
US-9,514,032 Real-time usage checking of dynamically generated program output
Receive output dynamically generated by a running program and check that output for spelling, grammar, and/or other usage errors, providing notice to a user of...
US-9,514,031 Auto-deployment and testing of system application test cases in remote server environments
A method for executing a system application test case of a runtime system in a server integrated environment is provided. The method includes establishing a...
US-9,514,030 Dynamic tracing framework for debugging in virtualized environments
Embodiments of the present invention provide a system and method for a dynamic tracing framework for debugging in a virtualized environment. Embodiment of the...
US-9,514,029 Partial recording of a computer program execution for replay
A method, system and program product for recording a program execution comprising recording processor context for each thread of the program, results of system...
US-9,514,028 System and method for determining correct execution of software based on baseline and real time trace events
An embodiment provides a level of assurance regarding correct operation of software. An embodiment creates baseline and real-time measurements of software and...
US-9,514,027 Context-aware model-driven hierarchical monitoring metadata
Metrics are defined and collected for an application. The metrics are organized in hierarchical trees with metrics aggregated at each node in the trees. Each...
US-9,514,026 Debugging analysis in running multi-user systems
Various arrangements for debugging logic being executed by a webserver is presented. A virtual machine of the webserver may execute runtime threads for a...
US-9,514,025 Modeling memory use of applications
A method includes receiving a program code at a processor. The method also includes generating, via the processor, a heap model corresponding to the program...
US-9,514,024 Agentless data collection
Tools and techniques for collecting data from target systems without the need for installation of expensive and high-maintenance software agents on the target...
US-9,514,023 Message flow control in a multi-node computer system
Embodiments of the invention provide for controlling message flow across a parallel computer system having multiple compute nodes by selectively grouping...
US-9,514,022 Modeling storage system performance
A system and method for creating an accurate black-box model of a live storage system and for predicting performance of the storage system under a given...
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