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Patent # Description
US-9,520,386 Light source unit and backlight assembly having the same
A method of protecting an LED chip from damage by ESD and EMI when the LED chip is housed in a light-emitting diode(s) housing package (LED package) and the LED...
US-9,520,385 Package structure and method for forming same
A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the...
US-9,520,384 Light-emitting device
A light-emitting device, having an overall color temperature when emitting light, includes a carrier, a first LED unit, and a second LED unit. The carrier has a...
US-9,520,383 Light emitting device package and lighting system
Disclosed is a light emitting device package and a lighting system. The light emitting device package includes a body, a first lead frame on the body, a...
US-9,520,382 Retrofit LED lamp with warm-white, more particularly flame-like white light
The invention relates to an LED lamp for warm white light having an LED module consisting of at least one color-converted blue or UV LED, and at least one...
US-9,520,381 Semiconductor device for use in flip-chip bonding, which reduces lateral displacement
A semiconductor device includes multilayer chips in which a first semiconductor chip and a second semiconductor chip are bonded together. A first electrode pad...
US-9,520,380 Wafer process for molded chip scale package (MCSP) with thick backside metallization
A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a...
US-9,520,379 Method of forming bump structure having a side recess and semiconductor structure including the same
In some embodiments, the present invention relates to a method of integrated chip bonding. The method forms a conductive trace on a surface of a first work...
US-9,520,378 Thermal matched composite die
A thermal matched composite material, suitable for use as a die is described. In one example, the material includes a metal plate and a substrate having a...
US-9,520,377 Semiconductor device package including bonding layer having Ag.sub.3Sn
Semiconductor device packages and methods of manufacturing the semiconductor device packages are provided. A semiconductor device package may include a bonding...
US-9,520,376 Bumpless build-up layer package including an integrated heat spreader
An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die...
US-9,520,375 Method of forming a solder bump on a substrate
A method of forming a solder bump on a substrate includes: forming a conductive layer(s) on the substrate having a surface on which an electrode pad is...
US-9,520,374 Semiconductor device, substrate and semiconductor device manufacturing method
The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor...
US-9,520,373 Semiconductor package
Provided is a semiconductor package including a semiconductor chip having one surface on which chip pads are formed, and a redistribution structure formed on...
US-9,520,372 Wafer level package (WLP) and method for forming the same
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad...
US-9,520,371 Planar passivation for pads
Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the...
US-9,520,370 Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor...
A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the...
US-9,520,369 Power module and method of packaging the same
Provided are a power module having an integrated power semiconductor and a method of packaging the same. The power module according to an aspect of the present...
US-9,520,368 Integrated circuit system having stripline structure
An integrated circuit system having: (A) a semiconductor chip with a signal strip conductor disposed on an upper surface of the chip; an active semiconductor...
US-9,520,367 Trenched Faraday shielding
A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a...
US-9,520,366 Chip comprising a phase change material based protecting device and a method of manufacturing the same
An electronic chip including an integrated circuit arranged a face of a substrate, and a protection device arranged partially facing the integrated circuit is...
US-9,520,365 Semiconductor device and method for forming semiconductor package having build-up interconnect structure over...
A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and...
US-9,520,364 Front side package-level serialization for packages comprising unique identifiers
A method of making a semiconductor device can include providing a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and...
US-9,520,363 Forming CMOSFET structures with different contact liners
A method of making a semiconductor device includes forming a first trench contact over a first source/drain region of a first transistor; forming a second...
US-9,520,362 Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of...
US-9,520,361 Semiconductor devices
Semiconductor devices are provided. A semiconductor device includes a substrate, a first conductive structure on the substrate, and a second conductive...
US-9,520,360 Angled ion beam processing of heterogeneous structure
A method for fabricating a multilayer structure includes providing a mask on a device stack disposed on the substrate, the device stack comprising a first...
US-9,520,359 Semiconductor device, display driver integrated circuit including the device, and display device including the...
A semiconductor device, which may be included in a display driver integrated circuit (IC) and a display device, includes a first interconnection and a second...
US-9,520,358 Via structure for optimizing signal porosity
An apparatus including a conductive stack structure includes an M.sub.x layer interconnect on an M.sub.x layer and extending in a first direction on a first...
US-9,520,357 Anti-fuse structure and method for manufacturing the same
A method for manufacturing a semiconductor device includes forming a fin extending between first and second pads on a substrate, removing a central portion of...
US-9,520,356 Circuit with reduced noise and controlled frequency
A die is packaged by flip-chip mounting the die with the active side facing a low loss substrate. A ground plane is coupled to the active side of the die by...
US-9,520,355 Voltage and temperature independent MIM capacitors
MIM capacitors that are temperature and/or voltage independent, and a methodology for formulating the MIM capacitors for use in semiconductor integrated...
US-9,520,354 Silicon designs for high voltage isolation
An isolation system, isolation capacitor, and Integrated Circuit are disclosed. The isolation capacitor is described to include a first capacitive element, a...
US-9,520,353 Metal-insulation-metal device
A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided....
US-9,520,352 Wiring board and semiconductor device
A wiring board includes a first wiring layer, a first insulating layer, first via wirings, connection terminals and a protection layer. The first insulating...
US-9,520,351 Packaging substrate and package structure
A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in...
US-9,520,350 Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer
Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die...
US-9,520,349 Semiconductor package
A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. A conductive trace is disposed on the substrate. A...
US-9,520,348 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is...
US-9,520,347 Lead frame construct for lead-free solder connections
An electronics packaging arrangement, a lead frame construct for use in an electronics packaging arrangement, and a method for manufacturing an electronics...
US-9,520,346 Power semiconductor module and method for manufacturing the same
The present invention relates to a power semiconductor module in which heat from the semiconductor chip is radiated not only through the buffer, but also...
US-9,520,345 Semiconductor module, semiconductor device having semiconductor module, and method of manufacturing...
A semiconductor module is configured such that heat radiation substrates are connected to lead frames and semiconductor chips are directly connected to the lead...
US-9,520,344 Semiconductor module for electric power
Included are: the third frame which is electrically connected to the first intermediate frame and is arranged above the first frame; the fourth frame which is...
US-9,520,343 Field-effect transistor structure for preventing from shorting
A field-effect transistor (FET) structure for preventing from shorting is disclosed. The field-effect transistor (FET) structure is applying to a power discrete...
US-9,520,342 Power management applications of interconnect substrates
Various applications of interconnect substrates in power management systems are described.
US-9,520,341 Semiconductor package with conductive clips
One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor...
US-9,520,340 Semiconductor die connection system and method
A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second...
US-9,520,339 Semiconductor device and method of manufacturing the same
According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the...
US-9,520,338 Transistor, heat sink structure thereof and method for manufacturing same
A transistor is provided, which includes: a semiconductor growth substrate and a semiconductor thermoelectric effect device, wherein the semiconductor...
US-9,520,337 Semiconductor module
A semiconductor module includes first and second semiconductor elements connected to pins, respectively; a first pin wiring substrate having first and second...
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