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Patent # Description
US-9,525,087 Light receiving device and method for manufacturing light receiving device
A light receiving device includes a mesa structure including a light absorption layer disposed on a semiconductor region; a passivation film disposed on a side...
US-9,525,086 Method of preparing metal nanoparticles for solar cell, ink composition including the metal nanoparticles, and...
Disclosed are a method of preparing metal nanoparticles for solar cells, an ink composition including the metal nanoparticles, and a method of preparing a thin...
US-9,525,085 Bismuth ferrite thin-film solar cell and method of manufacturing the same
A bismuth ferrite thin-film solar cell and a method of manufacturing the same control the quantity of Fe.sup.2+ defected in the bismuth ferrite thin-film by...
US-9,525,084 Microstructure enhanced absorption photosensitive devices
Techniques for enhancing the absorption of photons in semiconductors with the use of microstructures are described. The microstructures, such as holes,...
US-9,525,083 Solar cell emitter region fabrication with differentiated P-type and N-type architectures and incorporating a...
Methods of fabricating solar cell emitter regions with differentiated P-type and N-type architectures and incorporating a multi-purpose passivation and contact...
US-9,525,082 Solar cell contact structures formed from metal paste
Solar cell contact structures formed from metal paste and methods of forming solar cell contact structures from metal paste are described. In a first example, a...
US-9,525,081 Method of forming a bifacial solar cell structure
A method of forming bifacial solar cell structure is described. The method comprises: performing boron diffusion on an upper surface of a semiconductor...
US-9,525,080 Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of...
A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a...
US-9,525,079 Photoelectrical coversion module
A photoelectrical conversion module includes at least one photoelectrical conversion device, at least one first ribbon, a second ribbon, and at least two...
US-9,525,078 Tunable device having a FET integrated with a BJT
A device includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET...
US-9,525,077 Integration of a baritt diode
A vertically oriented BARITT diode is formed in an integrated circuit. The BARITT diode has a source proximate to the top surface of the substrate of the...
US-9,525,076 Memory device using graphene as charge-trap layer and method of operating the same
A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive...
US-9,525,075 Array substrate, method for manufacturing the same, and display device
An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed...
US-9,525,074 Display substrates, methods of manufacturing the same and display devices including the same
A display substrate includes a base substrate, a switching device on the base substrate and an alignment pattern. The switching device includes an active...
US-9,525,073 Semiconductor device including oxide semiconductor
A semiconductor device which occupies a small area is provided. A semiconductor device includes a resistor. The resistor includes a transistor. The increase...
US-9,525,072 Semiconductor device and method of formation
A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second...
US-9,525,071 Flexible high-voltage thin film transistors
A flexible high-voltage thin-film transistor includes a gate electrode, a source electrode, a drain electrode, a dielectric layer, and a flexible semiconductor...
US-9,525,070 TFT substrate structure and manufacturing method thereof
The present invention provides a TFT substrate structure and a manufacturing method thereof. A metal oxide semiconductor layer is formed on an amorphous silicon...
US-9,525,069 Structure and method to form a FinFET device
A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX)...
US-9,525,068 Variable gate width FinFET
An improved FinFET has a gate structure on only a portion of the available surface on a fin, thereby providing a FinFET with a finer granularity width...
US-9,525,067 Method for forming integrated circuits on a strained semiconductor substrate
An electronic circuit on a strained semiconductor substrate, includes: electronic components on a first surface of a semiconductor substrate; and at least...
US-9,525,066 Semiconductor device and manufacturing method thereof
Provided is a technique for promoting miniaturization of a MISFET. A p-type well region is disposed between LDDs (n-type low-concentration regions) of a MISFET...
US-9,525,065 Semiconductor devices including a channel pad, and methods of manufacturing semiconductor devices including a...
Semiconductor devices are provided. A semiconductor device includes a stack of gate electrodes. The semiconductor device includes a channel material in a...
US-9,525,064 Channel-last replacement metal-gate vertical field effect transistor
A method of making a vertical transistor includes forming a doped source on a substrate; depositing a sacrificial gate material on the source; forming a trench...
US-9,525,063 Switching circuit
In an embodiment, a switching circuit includes input drain, source and gate nodes, a high voltage depletion mode transistor including a current path coupled in...
US-9,525,062 Insulated gate switching element
An insulated gate switching element includes: a semiconductor substrate; a gate insulating film disposed on a surface of the semiconductor substrate; and a gate...
US-9,525,061 Semiconductor device including an n-well structure
A device comprising a p-type base region, and a p-type region formed over the p-type base region and in contact with the p-type base region is disclosed. The...
US-9,525,060 Reduced area power devices using deep trench isolation
An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with...
US-9,525,059 Semiconductor device with graded drift region
A semiconductor device includes a semiconductor layer that has a first surface and a second surface, a drift region of a first conductivity type in the...
US-9,525,058 Integrated circuit and method of manufacturing an integrated circuit
An integrated circuit includes a power component including a plurality of first trenches in a cell array and a first conductive material in the first trenches...
US-9,525,057 Semiconductor device
A source region of a MOSFET includes: a source contact region connected to a source pad; a source extension region adjacent to a channel region in a well...
US-9,525,056 Vertical microelectronic component and corresponding production method
A vertical microelectronic component includes a semiconductor substrate having a front side and a back side, and a multiplicity of fins formed on the front...
US-9,525,055 High-electron-mobility transistors
High-electron-mobility transistors that include field plates are described. In a first implementation, a HEMT includes a first and a second semiconductor...
US-9,525,054 High electron mobility transistor and method of forming the same
A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band...
US-9,525,053 Integrated circuit devices including strained channel regions and methods of forming the same
Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include...
US-9,525,052 Active area shaping of III-nitride devices utilizing a field plate defined by a dielectric body
In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a...
US-9,525,051 Semiconductor device and driving method thereof
A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which...
US-9,525,049 Method for fabricating fin field effect transistors
A method of fabricating a Fin field effect transistor (FinFET) includes providing a substrate having a first fin and a second fin extending above a substrate...
US-9,525,048 Symmetrical extension junction formation with low-k spacer and dual epitaxial process in finFET device
A technique relates to a dual epitaxial process a device. A first spacer is disposed on a substrate, dummy gate, and hardmask. A first area extends in a first...
US-9,525,047 Thin-film transistor substrate, method of manufacturing same, and organic light-emitting display apparatus...
A thin film transistor (TFT) substrate, an organic light-emitting display apparatus including the TFT substrate, and a method of manufacturing the TFT substrate...
US-9,525,046 Metal gate stack structure and manufacturing method
A gate electrode and method for manufacturing the same includes an amorphous gate metal layer. The amorphous gate metal layer includes an amorphous metal alloy...
US-9,525,045 Semiconductor devices and methods for forming the same
A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate having a first conductive type and an...
US-9,525,044 Method of manufacturing a spacer supported lateral channel FET
A semiconductor device is manufactured by forming a plurality of trenches extending into a semiconductor material from a first main surface of the semiconductor...
US-9,525,043 Semiconductor device and method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device includes forming a trench in a semiconductor body. The method further includes doping a part of the...
US-9,525,042 Semiconductor devices and methods for fabricating the same
A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a...
US-9,525,041 Semiconductor process for forming gates with different pitches and different dimensions
A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a...
US-9,525,040 Method of fabricating hybrid impact-ionization semiconductor device
A method includes providing a semiconductor substrate having an active region and forming an isolation structure to isolate the active region. First and second...
US-9,525,039 Method of fabricating a merged P-N junction and schottky diode with regrown gallium nitride layer
A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a...
US-9,525,038 Method for producing semiconductor device and semiconductor device
A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first...
US-9,525,037 Fabricating method of trench gate metal oxide semiconductor field effect transistor
A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly...
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