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Trapping dislocations in high-mobility fins below isolation layer
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect...
Switching system and method
The invention relates to a Radio Frequency System and method. A Radio Frequency (RF) system comprising a RF switch comprising a plurality of transistor...
3D semiconductor device with enhanced performance
The present disclosure may provide a semiconductor device with a low manufacturing degree of difficulty and an enhanced performance. The device may include...
Vertical memory devices
A vertical memory device includes a substrate, gate lines, channels, contacts and contact spacers. The gate lines are stacked on top of each other on the...
According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first...
Three dimensional memory device with hybrid source electrode for wafer
The metallic material content of a contact via structure for a three-dimensional memory device can be reduced by employing a vertical stack of a doped...
U-shaped vertical thin-channel memory
A memory device, which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks...
Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on...
3D non-volatile memory device and method of manufacturing the same
A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair...
Metal-semiconductor alloy region for enhancing on current in a
three-dimensional memory structure
Resistance of a semiconductor channel in three-dimensional memory stack structures can be reduced by forming a metal-semiconductor alloy region between a...
Method of integrating select gate source and memory hole for
three-dimensional non-volatile memory device
A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width...
Semiconductor device and method of manufacturing the same
Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device may include a dummy structure formed on a peripheral region...
Alternating sidewall assisted patterning
A dielectric layer extending over a substrate has alternating first and second trenches extending in a first direction. The first trenches have a first shape in...
Shallow trench air gaps and their formation
A method of forming a NAND flash memory includes etching between word lines to expose isolation material in shallow trench isolation (STI) trenches while active...
Metal layers for a three-port bit cell
An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to...
Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor...
Asymmetric semiconductor memory device having electrically floating body
Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described...
Integrated circuit having strained fins on bulk substrate
A method includes forming a set of fins composed of a first semiconductor material. The method further heats the set of fins to condense the fins and cause...
Semiconductor device having metal gate and fabrication method thereof
A fabrication method of semiconductor device having metal gate includes providing a substrate, successively forming a gate insulating layer and a bottom barrier...
Semiconductor device and method of forming the same
A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first transistor, a second transistor and a third...
The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor...
Gate structures with various widths and method for forming the same
Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a...
Capacitor structure in an integrated circuit
In an example, a capacitor in an integrated circuit (IC), includes: a first finger capacitor formed in at least one layer of the IC having a first bus and a...
A semiconductor device comprising: a first, a second and a third conductive layer; the second conductive layer being located between the first and third...
Semiconductor device comprising an e-fuse and a FET
A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on...
In the semiconductor device including the off transistor serving as an ESD protection element and an output element between a first external connection terminal...
Vertical transistor with flashover protection
Technologies are generally described for increase of spacing between source and drain regions of a vertical high voltage transistor without a significant...
System on integrated chips and methods of forming same
An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the...
Semiconductor device and method of individual die bonding followed by
simultaneous multiple die thermal...
A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or ...
Back-to-back stacked dies
Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a...
Integrated fan-out structure and method
A semiconductor package comprises a top package and a bottom package with fan-out interconnect structures. A plurality of inter-package connectors electrically...
Semiconductor device and method of forming no-flow underfill material
around vertical interconnect structure
A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow...
LED-based light sources for light emitting devices and lighting
arrangements with photoluminescence wavelength...
An LED-based light source for generating light having a selected dominant wavelength .lamda..sub.ds comprises a package housing a plurality of LEDs consisting...
In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an...
A semiconductor system may include first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data...
Semiconductor assembly comprising chip arrays
A semiconductor assembly includes a frame having at least one opening, an identical number of electrically conductive first contact plates, and an identical...
Stacked microelectronic packages having sidewall conductors and methods
for the fabrication thereof
A method for fabricating a stacked microelectronic device includes attaching a first package layer to a second package layer to form stacked microelectronic...
Semiconductor device having semiconductor chip affixed to substrate via
insulating resin adhesive film
A semiconductor device includes a semiconductor chip provided with a plurality of bumps arranged in a peripheral alignment, a substrate provided with a...
A package structure, comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die,...
Microelectronic interconnect element with decreased conductor spacing
A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal...
An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted...
Cu pillar bump with L-shaped non-metal sidewall protection structure
An L-shaped sidewall protection process is used for Cu pillar bump technology. The L-shaped sidewall protection structure is formed of at least one of non-metal...
Method for fabricating package structure
A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer...
Compact semiconductor package and related methods
A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element...
Chip-on-substrate packaging on carrier
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a...
Power semiconductor housing with redundant functionality
In various embodiments, a power semiconductor housing having an integrated circuit is provided. The integrated circuit may include: a first gate pad and a...
Method for manufacturing a semiconductor device, and semiconductor device
According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at...
Multiple edge enabled patterning
Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum...
Package-in-package using through-hole via die on saw streets
A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is...
Semiconductor devices and methods of fabricating the same
Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable...