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Patent # Description
US-9,524,936 Power semiconductor module and method for manufacturing the same
A power semiconductor module may include a first device and a second device spaced apart from the first device at a predetermined interval. A first assembling...
US-9,524,935 Filling cavities in an integrated circuit and resulting devices
A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include...
US-9,524,934 Integrated circuits with electrical fuses and methods of forming the same
A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate...
US-9,524,933 Semiconductor structures and fabrication methods thereof
A method for forming a semiconductor structure including providing a substrate; forming a dielectric layer covering a surface of the substrate; forming a...
US-9,524,932 Semiconductor device with combined passive device on chip back side
Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the...
US-9,524,931 Wiring substrate, semiconductor package, and method for manufacturing semiconductor package
A wiring substrate includes a block with substrates laid out in an array. The block includes corners and a plan view center. Each substrate includes a substrate...
US-9,524,930 Configurable interposer
A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two...
US-9,524,929 Semiconductor module package and method of manufacturing the same
There is provided a semiconductor module package including: a base substrate formed by mounting one or more first semiconductor devices thereon; a lead frame...
US-9,524,928 Power quad flat no-lead (PQFN) package having control and driver circuits
According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a multi-phase power inverter, a control circuit, and a driver...
US-9,524,927 Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for...
Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or...
US-9,524,926 Packaged device with additive substrate surface modification
A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a...
US-9,524,925 Method of manufacturing a semiconductor device
There is provided a method for manufacturing a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that...
US-9,524,924 Dielectric cover for a through silicon via
An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical...
US-9,524,923 Semiconductor structure and method for manufacturing the same
A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a substrate, a through silicon via hole,...
US-9,524,922 Integrated circuit having main route and detour route for signal transmission and integrated circuit package...
The integrated circuit includes first and second vias, a first buffer configured to receive a signal transmitted from the first via, a second buffer configured...
US-9,524,921 Semiconductor device and method for fabricating the same
A semiconductor device and a method for fabricating the same are provided. The semiconductor device comprising a substrate including a first surface and a...
US-9,524,920 Apparatus and method of three dimensional conductive lines
An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a...
US-9,524,919 Semiconductor module and semiconductor device
A semiconductor module includes a semiconductor element having a gate electrode and source electrode on the front surface, and a drain electrode on the rear...
US-9,524,918 Heat dissipating component for semiconductor element
Disclosed is a heat dissipating component for a semiconductor element, having a tabular body 0.4-6 mm in thickness containing 40-70 volume % of diamond...
US-9,524,917 Chip level heat dissipation using silicon
A semiconductor device that includes a semiconductor chip having a first silicon substrate with opposing first and second surfaces, a semiconductor device...
US-9,524,916 Structures and methods for determining TDDB reliability at reduced spacings using the structures
A structure for TDDB measurement, a method determining TDDB at reduced spacings. The structure includes an upper dielectric layer on a top surface of a lower...
US-9,524,915 Semiconductor device
A mask includes a substrate, an effective pixel formation region and a reference pattern formation region. A pixel pattern for forming a pixel component that...
US-9,524,914 Method of manufacturing organic EL display apparatus, and inspection apparatus
A method of manufacturing an organic EL display apparatus including an organic EL panel having light emitting pixels each of which has an organic EL element...
US-9,524,913 Polishing method and polishing apparatus
A polishing method and a polishing apparatus for performing a measurement of a film thickness of a substrate, such as a wafer, if an error has occurred during...
US-9,524,912 Methods for forming CMOS inverters
A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first...
US-9,524,911 Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC device
Methods for creating self-aligned FINFET SDBs for minimum gate junction pitch and epitaxy formation. Embodiments include forming separated openings in a hard...
US-9,524,910 Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor...
US-9,524,909 Fin structure and fin structure cutting process
A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin...
US-9,524,908 Methods of removing portions of fins by preforming a selectively etchable material in the substrate
One illustrative method disclosed herein includes, among other things, forming a region of a sacrificial material in a semiconductor substrate at a location...
US-9,524,907 Top metal pads as local interconnectors of vertical transistors
An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first...
US-9,524,906 Semiconductor device and manufacturing method thereof
A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer...
US-9,524,905 Nitrided tungsten via
A nitridation step applied to a tungsten via in a first silicon oxide layer forms a tungsten nitride layer on an exposed top surface of the tungsten via....
US-9,524,904 Early bit line air gap formation
Dummy bit lines of are formed in a sacrificial layer at locations where bit lines are to be formed, with bit lines separated by trenches that extend through the...
US-9,524,903 Interconnection structure, semiconductor device, and method of manufacturing the same
An interconnection structure may include insulating layers stacked stepwise and dielectric layers interposed between the insulating layers. The interconnection...
US-9,524,902 Method of forming integrated circuit with conductive line having line-ends
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is deposited over a substrate and a hard mask (HM) layer is...
US-9,524,901 Multiheight electrically conductive via contacts for a multilevel interconnect structure
A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of...
US-9,524,900 Silicon-on-insulator microchannels for biological sensors
Novel methods to fabricate biological sensors and electronics are disclosed. A silicon-on-insulator wafer can be employed by etching a pattern of holes in the...
US-9,524,899 Semiconductor device having multiple wells for low- and high-voltage CMOS transistors
There are included: forming element isolation regions in a semiconductor substrate; introducing a first impurity of a first conductivity type, to thereby form a...
US-9,524,898 Monolithic integration techniques for fabricating photodetectors with transistors on same substrate
Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a...
US-9,524,897 End handler for film and film frames and a method thereof
An end handler and method for processing a device are presented. The end handler includes a mating portion for mating with a tool and a support portion for...
US-9,524,896 Apparatus and methods for transporting and processing substrates
There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved...
US-9,524,895 Substrate transfer antechamber mechanism
There is provided a substrate transfer antechamber mechanism for a compact manufacturing apparatus that produces various types of devices in small volume using...
US-9,524,893 Inactive gas introducing facility and inactive gas introducing method
An inactive gas introducing facility includes an introducing device disposed in a support portion supporting a container accommodating a substrate and...
US-9,524,892 Semiconductor stocker systems and methods
In an embodiment, the present invention discloses cleaned storage processes and systems for high level cleanliness articles, such as extreme ultraviolet (EUV)...
US-9,524,891 Apparatus for fixing metal mask
An apparatus for fixing a metal mask includes a first substrate, a magnet array structure, a second substrate, and a metal mask. The magnet array structure...
US-9,524,890 Computer visual recognition output image-aided LED die sorting system and sorting method
The invention relates to computer visual recognition output image-aided LED die sorting system and sorting method. The computer visual recognition output...
US-9,524,889 Processing systems and apparatus adapted to process substrates in electronic device manufacturing
A via pass-through apparatus is disclosed. The via pass-through apparatus includes a pass-through chamber adapted to couple between a first mainframe section...
US-9,524,888 Stage heater and method of manufacturing shaft
A stage heater and a method of manufacturing a shaft capable of suppressing heat transfer from a heating substrate toward the shaft. The stage heater includes:...
US-9,524,887 Etching apparatus for substrate and method of etching using the same
An etching apparatus includes a receiving container which receives a substrate, and a first spraying unit which supplies etchant into the receiving container....
US-9,524,886 Brush core and brush driving method
A brush core for engaging and rotating a generally cylindrical brush having a hollow bore is provided. The brush core includes, but is not limited to, a body...
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