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Patent # Description
US-9,524,280 Method and system to automatically insert a relevant hyperlink into a webpage
A method and system to automatically insert a hyperlink into a webpage containing text is described. The system comprises at least one processor and at least...
US-9,524,279 Help document animated visualization
Data for performing help document animated visualization is obtained by generating operation records from a text-based help document of an application. Each of...
US-9,524,278 Systems and methods to present content
A content presentation system in which a set of content items, which may include static stored content documents and/or live content streaming from computing...
US-9,524,277 Execution and display of events in a plurality of web browsers and devices systems and method
There is provided systems and method for an execution and display of events in a plurality of web browsers and devices. The methods include receiving an event...
US-9,524,276 Bookmarking social networking system content
A social networking system allows users to bookmark content within the social networking system to view at a later time and/or to share with other users. The...
US-9,524,275 Selectively translating specified document portions
Methods, systems and computer program products are provided for selectively translating documents. For example, a computer system may be provided that...
US-9,524,274 Methods and systems for generation of document structures based on sequential constraints
Disclosed is a method that structures a sequentially-ordered set of elements, each being characterized by a set of features. N-grams (sequence of n features)...
US-9,524,273 Method and system for generating a web page layout using nested drop zone widgets having different software...
Therefore, what has been described is an improved for visually implementing a web page layout, where the web page layout includes a nested drop zone. Allowing...
US-9,524,272 Navigating among content items in a browser using an array mode
In any context where a user can view multiple different content items, switching among content items is provided using an array mode. In a full-frame mode, one...
US-9,524,271 Distributed computation of linear combinations in a network
A first source node transmits a first transmission vector formed by multiplying a vector of input values and an inverse of a transfer matrix that relates...
US-9,524,270 Operand-optimized asynchronous floating-point units and method of use thereof
Asynchronous arithmetic units including an asynchronous IEEE 754 compliant floating-point adder and an asynchronous floating point multiplier component....
US-9,524,269 Driving event data analysis
A driving analysis server may be configured to receive vehicle operation data from vehicle sensors, and may use the data to identify a potentially high-risk or...
US-9,524,268 Vestibular dynamic inclinometer
A method of determining orientation parameters of a rigid body, including: associating at least two multi-axis accelerometers with the rigid body, wherein the...
US-9,524,267 Check operation dispersed storage network frame
A method begins by a processing module generating a payload section of a dispersed storage network (DSN) frame regarding a check request operation by generating...
US-9,524,266 Latency management system and method for multiprocessor system
A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared...
US-9,524,265 Providing a serial protocol for a bidirectional serial interconnect
In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect...
US-9,524,264 Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems,...
Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and ...
US-9,524,263 Method and apparatus for bus lock assistance
A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution...
US-9,524,262 Connecting expansion slots
Example embodiments disclosed herein relate to selectively connecting an interconnect bus to an expansion slot. A first chip is connected to a first...
US-9,524,261 Credit lookahead mechanism
Systems and methods for preventing excessive buffering of transactions in a coherence point. The coherence point uses a lookahead mechanism to determine if...
US-9,524,260 Universal serial bus (USB) communication systems and methods
Universal serial bus (USB) communication systems and methods are disclosed. In particular, aspects of the present disclosure optimize polling and scheduling of...
US-9,524,259 Method for operating an automation device to reduce dead time on account of a physical interruption in a ring...
A method for operating an automation device having a CPU module that is configured to effect read or write access to local peripherals that are each provided...
US-9,524,258 Method for controlling multiple CAN interfaces through single SPI bus
The disclosure is applied to a field of communication technologies and relates to a method for controlling multiple CAN interfaces through a single SPI bus. The...
US-9,524,257 Transactional execution enabled supervisor call interruption while in TX mode
A computer can manage an interruption while a processor is executing a transaction in a transactional-execution (TX) mode. Execution, in a program context, of...
US-9,524,256 Request controller, processing unit, arrangement, method for controlling requests and computer program product
An request controller for controlling requests of a processing unit. The request controller may include an request controller input for receiving an request and...
US-9,524,255 System and method for automatic DQS gating based on counter signal
Systems and methods for timing read operations with a memory device are provided. A timing signal from the memory device is received at a gating circuit. The...
US-9,524,254 Multi-serial interface stacked-die memory architecture
Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding...
US-9,524,253 Method of selecting air interface at ambient connectivity and hub using said method
A method of selecting an interface by a hub, includes searching for a device of the hub, and measuring a distance from the hub to the device based on...
US-9,524,252 Input system and method
An input system includes a communication device and a first input device. The communication device includes a communication chip and a communication port. The...
US-9,524,251 Storage system, virtualization control apparatus, information processing apparatus, and method for controlling...
An information processing apparatus is configured to make access to a storage device via a first path. A virtualization control apparatus is configured to...
US-9,524,250 Block or page lock features in serial interface memory
Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a...
US-9,524,249 Memory encryption engine integration
Memory encryption engine (MEE) integration technologies are described. A processor can include a processor core and an arbiter of a MEE system coupled to the...
US-9,524,248 Memory management for a hierarchical memory system
Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual...
US-9,524,247 Fractured erase system and method
Efficient and convenient storage systems and methods are presented. In one embodiment, a fractured erase process is performed in which a pre-program process,...
US-9,524,246 Resetting memory locks in a transactional memory system
A system and computer program product for resetting of memory locks in a transactional memory system. The system includes a processor setting at least one new...
US-9,524,245 Cache management method and apparatus for non-volatile storage device
Embodiments of the present invention disclose a method and apparatus of cache management for a non-volatile storage device. The method embodiment includes:...
US-9,524,244 Write cache destaging
Disclosed is a system for controlling write actions to a plurality of data storage devices, the system comprising a plurality of write caches, wherein each...
US-9,524,243 Scalable monolithic data storage system for cloud environment
A scalable, storage cloud enabled data center includes a cluster of enterprise storage nodes. Each storage node includes a storage grid, a computation grid, and...
US-9,524,242 Cache memory system with simultaneous read-write in single cycle
A cache includes a number of cache ways each having tag memory fields and corresponding data fields. With a simultaneous read-write operation defined by a read...
US-9,524,241 Multi-core microprocessor power gating cache restoral mechanism
An apparatus includes a fuse array and a stores. The fuse array is disposed on a die, and is programmed with compressed configuration data for a plurality of...
US-9,524,240 Obscuring memory access patterns in conjunction with deadlock detection or avoidance
Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock...
US-9,524,239 Self service propagation of custom extension fields into web services
Software solutions in a business software framework can expose their data via web services, which can readily provide access to all non-customized fields of...
US-9,524,238 Systems and methods for managing cache of a data storage device
A data storage device includes a data storage medium, a cache, and a cache control memory. The data storage medium has M data blocks. M is an integer greater...
US-9,524,237 Data processing device and semiconductor intergrated circuit device for a bi-endian system
The present invention provides a data processing device where a program can be commonly used and a vector table can be shared regardless of types of endian in a...
US-9,524,236 Systems and methods for performing memory management based on data access properties
Systems and methods are provided for performing memory management in a storage device. The systems and methods may include receiving, at the storage device, a...
US-9,524,235 Local hash value generation in non-volatile data storage systems
The various implementations described herein include systems, methods and/or devices used to enable local hash value generation in a non-volatile data storage...
US-9,524,234 System and method for optimizing memory usage in a universal controlling device
A method for optimizing memory usage in a device having a universal controlling application includes receiving into the device data for use in configuring the...
US-9,524,233 System and method for efficient swap space allocation in a virtualized environment
A technique for efficient swap space management creates a swap reservation file using thick provisioning to accommodate a maximum amount of memory reclamation...
US-9,524,232 Inter-core cooperative TLB prefetchers
A chip multiprocessor includes a plurality of cores each having a translation lookaside buffer (TLB) and a prefetch buffer (PB). Each core is configured to...
US-9,524,231 Software test automation system and method
A method for testing a software application is provided. The method may comprise associating a plurality of controls on a software application screen with...
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