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Three-dimensional memory devices having a single layer channel and methods
of making thereof
A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed...
Memory device and method for fabricating the same
Provided is a memory device including a stack structure, a plurality of first cap layers, and a plurality of second cap layers. The stack structure is located...
Method of manufacturing non-volatile memory having SONOS memory cells
A method for manufacturing a non-volatile memory with SONOS memory cells, which includes steps of: providing a substrate; forming a first gate oxide layer and a...
Nonvolatile semiconductor memory device comprising memory gate and
peripheral gate having different thicknesses
A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory element including a first gate electrode having a first thickness...
Three dimensional NAND memory having improved connection between source
line and in-hole channel material as...
A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without...
Memory bit cell for reduced layout area
An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and...
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure...
Semiconductor devices having metal gate and method for manufacturing
semiconductor devices having metal gate
Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device...
FinFETs of different compositions formed on a same substrate
Methods and structures for forming finFETs of different semiconductor composition and of different conductivity type on a same wafer are described. Some finFET...
FinFET semiconductor device with germanium diffusion over silicon fins
A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor...
Methods of forming different FinFET devices having different fin heights
and an integrated circuit product...
One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first...
Semiconductor package for III-nitride transistor stacked with diode
One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride...
Systems and methods for integrating bootstrap circuit elements in power
transistors and other devices
Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments,...
Methods of manufacturing devices including gates with multiple lengths
A method for manufacturing a semiconductor device comprises forming a first dummy gate layer on a substrate, forming a second dummy gate layer on the substrate...
Feedback and impedance circuits, devices and methods for broadband
Feedback and impedance circuits, devices and methods for broadband radio-frequency (RF) amplifiers. An RF amplifier architecture can include an amplifier having...
Integrated circuits with resistor structures formed from gate metal and
methods for fabricating same
Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a...
Semiconductor device with electro-static discharge protection device above
semiconductor device area
A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is...
Gate-coupled NMOS device for electro-static discharge protection
A gate-coupled NMOS device according to an embodiment includes a P-type well region, an N-type well region, and N-channel MOS transistor, an N+-type tap region,...
Semiconductor light emitting element
According to one embodiment, a semiconductor light emitting element includes a base body, first to sixth semiconductor layers, a first conductive layer, and a...
A transistor (2) is provided on a semiconductor substrate (8). A temperature detection diode (4) for monitoring temperature of an upper surface of the...
Distributing capacitance with gate driver for power switch
A semiconductor device includes a semiconductor die, a power switch, a gate driver, and decoupling capacitor. The power switch includes a power FET having a...
Semiconductor arrangement with active drift zone
A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load...
Monolithic integration of CMOS and non-silicon devices
A method includes attaching a partially processed CMOS wafer to a second wafer to produce a combined wafer. The second wafer comprises a first region including...
Semiconductor package, semiconductor device and method of forming the same
According to an exemplary embodiment, a semiconductor package is provided. The A semiconductor package includes at least one chip, and at least one component...
Package systems including passive electrical components
A package system includes at least one active circuitry disposed over a substrate. A passivation structure is disposed over the at least one active circuitry....
Light emitting device having plurality of light emitting elements and
light reflective member
A light emitting device includes: a base member; and a plurality of light emitting elements mounted on the base member. The plurality of light emitting elements...
3D package with through substrate vias
A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a...
3D integrated circuit package with through-mold first level interconnects
3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package...
Single mask package apparatus
Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the...
Semiconductor apparatus having electrical connections with through-via and
a metal layer and stacking method...
A semiconductor apparatus may include a first metal layer including a first unit pad. The semiconductor apparatus may include a second metal layer including...
Provided is a semiconductor package including a substrate, a first semiconductor chip disposed on the substrate to have a rectangular shape with long and short...
Chip package and chip assembly
A chip package is provided. The chip package may include an electrically conductive carrier; at least one first chip including a first side and a second side...
Integrated circuit packaging system with chip stacking and method of
A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting an integrated circuit structure on the first...
Method for forming electronic components
A method which comprises arranging a plurality of electronic chips in a plurality of chip accommodation cavities each defined by a respective surface portion of...
Die bonder and bonding method
A die bonder and a bonding method are provided that are capable of surely mounting a die on an intermediate stage and surely picking up the die from the...
Method of clamping a semiconductor assembly
The present invention relates to a method of clamping a semiconductor assembly with a desired compression force equally distributed across the opposing surfaces...
Coupling of side surface contacts to a circuit platform
An apparatus relates generally to a microelectromechanical system component. In such an apparatus, the microelectromechanical system component has a lower...
Packaged microelectronic devices and methods for manufacturing packaged
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
Solder in cavity interconnection structures
The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first...
Chip mounting structure and manufacturing method therefor
Chip mounting is provided in which the pitch between bumps can be further narrowed without establishing contact between bumps. In a chip mounting structure in...
Electronic apparatus and method for fabricating the same
An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and...
Semiconductor device and method of manufacturing the same
A semiconductor device includes a wiring substrate including a first electrode in which a cross-sectional shape is an inverted trapezoidal shape, a...
Integrated electronic device with transceiving antenna and magnetic
An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface,...
Semiconductor device with structural stability
The present disclosure provides a semiconductor device with a structural stability. The semiconductor device includes a stack of vertical alterations of...
Semiconductor packages having residual stress layers and methods of
fabricating the same
A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a...
3D interconnect structure comprising through-silicon vias combined with
fine pitch backside metal...
A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed...
Package on package (PoP) device comprising a high performance inter
A package on package (PoP) device includes a first package and a second package. The first package includes a first package substrate, a die coupled to the...
Semiconductor device and method of forming interconnect structure and
mounting semiconductor die in recessed...
A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An...
Semiconductor device and manufacturing method thereof
In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the...
Semiconductor device and formation thereof
A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug...