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Patent # Description
US-9,530,735 Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes forming stepped stack structures each including conductive patterns stacked in a shape of steps while...
US-9,530,734 Enforcement of semiconductor structure regularity for localized transistors and interconnect
A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG...
US-9,530,733 Forming layers of materials over small regions by selective chemical reaction including limiting enchroachment...
A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each...
US-9,530,732 Efficient layout placement of a diode
A semiconductor device includes a plurality of first wires and a plurality of second wires. Each of the first wires forms a closed polygon and surrounds a...
US-9,530,731 Method of optical proximity correction for modifying line patterns and integrated circuits with line patterns...
A method of optical proximity correction executed by a computer system for modifying line patterns includes the following steps. First, providing an integrated...
US-9,530,730 Configurable routing for packaging applications
Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die...
US-9,530,729 Semiconductor devices including insulating extension patterns between adjacent landing pads and methods of...
A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof...
US-9,530,728 Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming...
US-9,530,727 Conductive line routing for multi-patterning technology
A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage...
US-9,530,726 Semiconductor device and method of fabricating the same
A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion,...
US-9,530,725 Wiring substrate and semiconductor package
A wiring substrate includes a core layer including a plate-like body and linear conductors, a first wiring layer formed on a first surface of the plate-like...
US-9,530,724 Compact power quad flat no-lead (PQFN) package
Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical ...
US-9,530,723 Semiconductor device and manufacturing method thereof
On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the...
US-9,530,722 Semiconductor device and production method for same
The present invention relates to a power module obtained by connecting the opposite sides of a chip with solder, and prevents the side surfaces of a base...
US-9,530,721 Semiconductor device
A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A...
US-9,530,720 Monitor structures and methods of formation thereof
In accordance with an embodiment of the present invention, a method of forming an electronic device includes forming a first opening and a second opening in a...
US-9,530,719 Direct die solder of gallium arsenide integrated circuit dies and methods of manufacturing gallium arsenide wafers
Electronic devices, and methods of manufacturing the electronic devices, utilizing direct die soldering of GaAs integrated circuit dies. In some embodiments,...
US-9,530,718 DBF film as a thermal interface material
A die backside film including a matrix material; and an amount of filler particles to render the die backside film thermally conductive, wherein a thermal...
US-9,530,717 Bonded body and power module substrate
The bonded body of the present invention includes: a ceramic member made of ceramics; and a Cu member which is made of Cu or a Cu alloy and bonded to the...
US-9,530,716 Apparatus, system, and method for transferring heat from memory components
The apparatus to transfer heat from memory components includes a first non-volatile memory component and a second non-volatile memory component. The apparatus...
US-9,530,715 Thermally enhanced structure for multi-chip device
A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer...
US-9,530,714 Low-profile chip package with modified heat spreader
An integrated circuit system includes a heat spreader that is thermally coupled to a semiconductor chip and has a cavity or opening formed in the heat spreader....
US-9,530,713 Cooler-integrated semiconductor module
A cooler-integrated semiconductor module, includes an insulating substrate; a circuit layer disposed on a front surface of the insulating substrate; a...
US-9,530,712 Power electronic switching device and assembly
A switching device having a substrate, a power semiconductor component, a connecting device, load connection devices and a pressure device. Substrate has...
US-9,530,711 Silicon-on-insulator heat sink
An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a ...
US-9,530,710 Passivation structure of fin field effect transistor
A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first...
US-9,530,709 Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in...
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed...
US-9,530,708 Flexible electronic circuit and method for manufacturing same
An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered...
US-9,530,707 Semiconductor module
A semiconductor module includes a printed circuit board having an insulating plate, first and fourth wiring layers disposed on a principal surface of the...
US-9,530,706 Semiconductor devices having hybrid stacking structures and methods of fabricating the same
A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second...
US-9,530,705 4 port L-2L de-embedding method
Some embodiments relate to a wafer. The wafer includes a first dummy component comprising two or more first dummy component transmission lines. One of the first...
US-9,530,704 Polishing apparatus and wear detection method
There is provided a polishing apparatus capable of detecting uneven wear occurring on a polishing pad and detecting an appropriate replacement timing of the...
US-9,530,703 Method for manufacturing silicon carbide semiconductor device
Provided is a method for manufacturing a silicon carbide semiconductor device capable of preventing an increase in a cost of manufacturing one chip while...
US-9,530,702 Method for measuring recombination lifetime of silicon substrate
Provided is a method of measuring a recombination lifetime of a silicon substrate, which is capable of evaluating metal contamination and crystal defects in a...
US-9,530,701 Method of forming semiconductor fins on SOI substrate
An approach to forming fins for a semiconductor device on a silicon-on-insulator wafer. The approach includes depositing a layer of mandrel material and etching...
US-9,530,700 Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess etch
A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings...
US-9,530,699 Semiconductor device including gate channel having adjusted threshold voltage
A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor...
US-9,530,698 Method and structure for forming FinFET CMOS with dual doped STI regions
A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the...
US-9,530,697 Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor film, a memory film, an interconnect portion,...
US-9,530,696 Method of fabricating semiconductor device
A method of fabricating a semiconductor device is provided. A plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder...
US-9,530,695 Wafer processing method
A wafer processing method includes a wafer unit forming step of supporting a wafer through an adhesive tape to an annular frame to thereby form a wafer unit, a...
US-9,530,694 Method for fabricating semiconductor device having through silicon via
A semiconductor device includes a semiconductor substrate configured to include a circuit pattern at one surface, an insulation film formed over a back surface...
US-9,530,693 Semiconductor device and method of fabricating the same
A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a...
US-9,530,692 Method of forming through wiring
Provided is a method of forming a through wiring, including forming a first insulating film on a first surface and a second surface of a substrate; forming a...
US-9,530,691 Methods, apparatus and system for forming a dielectric field for dual orientation self aligned vias
At least one method, apparatus and system disclosed herein for forming an integrated circuit having a dual-orientation self aligned via. A first dielectric...
US-9,530,690 Metal pad structure over TSV to reduce shorting of upper metal layer
Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad...
US-9,530,689 Methods for fabricating integrated circuits using multi-patterning processes
Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes...
US-9,530,688 Directed self assembly of block copolymers to form vias aligned with interconnects
A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an...
US-9,530,687 Method of manufacturing bonded substrate, bonded substrate, method of manufacturing solid-state imaging...
Disclosed herein is a method of manufacturing a bonded substrate, including the steps of: forming a first bonding layer on a surface on one side of a...
US-9,530,686 MOS transistor and method of manufacturing the same
A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to...
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