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Patent # Description
US-9,530,532 Hybrid conductor with circumferential conducting layers
A conducting medium or high voltage cable can include at least one conductor surrounded by an insulating layer. One or more layers of conducting wires can...
US-9,530,531 Process for producing highly conducting and transparent films from graphene oxide-metal nanowire hybrid materials
A process for producing a transparent conductive film, comprising (a) providing a graphene oxide gel; (b) dispersing metal nanowires in the graphene oxide gel...
US-9,530,530 Scintillator panel, radiation detector, and methods for manufacturing the same
A method is provided for manufacturing a scintillator panel including a substrate and a scintillator layer containing a plurality of crystals formed by...
US-9,530,529 Radioisotope battery and manufacturing method thereof
This invention relates to a radioisotope battery and a method of manufacturing the same, wherein manufacturing the radioisotope battery and shielding radiation...
US-9,530,528 X-ray tube aperture having expansion joints
An x-ray tube electron shield is disclosed for interposition between an electron emitter and an anode configured to receive the emitted electrons. The electron...
US-9,530,527 Advanced fuel CRUD sampling tool method
A method to perform an analysis of two types of CRUD on a nuclear fuel rod, including providing a nuclear fuel rod with a first and second layer of CRUD on an...
US-9,530,526 Riser transition element for compact nuclear reactor
A nuclear reactor core is disposed in a pressure vessel along with upper internals disposed in the pressure vessel above the reactor core. The upper internals...
US-9,530,525 Locking fastener for securing components in a nuclear reactor
A threaded fastener includes a head, a threaded shank extending from a bottom face of the head along a longitudinal axis of the fastener, and an annular flange...
US-9,530,524 Localised energy concentration
A method of producing a localized concentration of energy comprises creating at least one shockwave (10) propagating through a non-gaseous medium (8) so as to...
US-9,530,523 Thermal disturb as heater in cross-point memory
The present disclosure relates to thermal disturb as heater in cross-point memory. An apparatus includes a memory controller. The memory controller is...
US-9,530,522 Sorting non-volatile memories
A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over...
US-9,530,521 Shift register unit, gate driving circuit, and display device
The present invention provides a shift register unit, a gate driving circuit and a display device. The shift register unit comprises: an input module for, in...
US-9,530,520 Shift register unit, GOA circuit, array substrate and display device
A shift register unit, a GOA circuit, an array substrate and a display device are provided. The shift register unit comprises an input module, a charging...
US-9,530,519 Scan driver and display device including the same
A scan driver and a display device including the scan driver are provided. The scan driver is configured to drive a plurality of pixels with a plurality of gate...
US-9,530,518 Semiconductor device
A control circuit controls execution of first-stage processing for increasing a threshold voltage of both or one of a first storage element and a second storage...
US-9,530,517 Read disturb detection in open blocks
A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from...
US-9,530,516 Readout of interfering memory cells using estimated interference to other memory cells
A method includes storing data in a memory that includes multiple analog memory cells. After storing the data, an interference caused by a first group of the...
US-9,530,515 Determining read voltages for reading memory
A method of reading data at a data storage device that includes a non-volatile memory includes identifying a first set of storage elements of a first word line...
US-9,530,514 Select gate defect detection
Detecting defects in select gates of memory cell strings is disclosed. An electrical short between adjacent select gates may be detected. The select gate may...
US-9,530,513 Methods and apparatus to read memory cells based on clock pulse counts
A disclosed example sense programmed states of memory cells includes starting a counter at a time of activating a plurality of memory cells. Binary values are...
US-9,530,512 Temperature dependent sensing scheme to counteract cross-temperature threshold voltage distribution widening
Methods for reducing cross-temperature threshold voltage distribution widening by applying a temperature dependent sensing scheme during read operations are...
US-9,530,511 Operating method of memory device
An operating method of a memory device includes providing the memory device and performing an erase operation. The memory device includes a substrate, a gate...
US-9,530,510 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a...
US-9,530,509 Data programming method, memory storage device and memory control circuit unit
A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the...
US-9,530,508 Memory device and method for operating the same
A memory device and a method for operating the same are provided. The memory device includes a substrate, a plurality of word lines, and a plurality of dummy...
US-9,530,507 Non-volatile memory apparatus and writing circuit and method for non-volatile memory apparatus
A writing circuit for a non-volatile memory apparatus is provided. The non-volatile memory apparatus includes a control circuit determining that a programming...
US-9,530,506 NAND boosting using dynamic ramping of word line voltages
Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may...
US-9,530,505 EEPROM memory cell gate control signal generating circuit
An EEPROM memory cell gate control signal generating circuit, which includes a high-voltage row decoding circuit and a plurality of word selection circuits; the...
US-9,530,504 Memory cells using multi-pass programming
A method is provided for programming non-volatile memory cells. The non-volatile memory cells are accessible by a plurality of word lines. The method includes...
US-9,530,503 And-type SGVC architecture for 3D NAND flash
A memory device includes a plurality of strings of memory cells. A plurality of stacks of conductive strips includes first upper strips configured as first...
US-9,530,502 Configuration memory storing data by injecting carriers in gate insulating layer of MISFET
A configuration memory includes: memory cell including first and second MISFETs, each of the first and second MISFETs having a gate insulating layer, a source,...
US-9,530,501 Non-volatile static random access memory (NVSRAM) having a shared port
A nonvolatile memory device includes a shared port block, a plurality of decoded address signals, a read signal, and a read word line. The shared port block...
US-9,530,500 Converting an XY TCAM to a value TCAM
Approaches for an integrated circuit ternary content addressable memory (TCAM) are provided. A system includes an array of XY TCAM cells and respective...
US-9,530,499 Semiconductor memory device and information processing device
According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory stores data pieces and search information including...
US-9,530,498 Optical data store and method for storage of data in an optical data store
An optical data store is specified, having a data storage layer with a non-toxic and biodegradable polymer as light-sensitive storage medium which has...
US-9,530,497 Systems, methods and devices for programming a multilevel resistive memory cell
Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and...
US-9,530,496 Method for programming switching element
In order to realize a switching element that is highly reliable and can be highly integrated, in a method for programming a switching element of the present...
US-9,530,495 Resistive switching memory having a resistor, diode, and switch memory cell
In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can...
US-9,530,494 Memory device and method of operating the same
A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each...
US-9,530,493 Resistive random-access memory cells
Improved random-access memory cells, complementary cells, and memory devices. The present invention provides a RRAM cell for storing information in a plurality...
US-9,530,492 NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program,...
Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL...
US-9,530,491 System and method for direct write to MLC memory
Apparatus and method for writing data directly to multi-level cell (MLC) memory without folding or transferring of the data from single-level cell (SLC) memory...
US-9,530,490 Compaction process for a data storage device
A data storage device may include a memory die. The memory die may include a memory. A method may include selecting a source compaction block of the memory for...
US-9,530,489 Optoelectronic device, in particular memory device
A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second...
US-9,530,488 Methods, apparatus and system determining dual port DC contention margin
At least one method, apparatus and system disclosed involves testing a dual port memory cell in a memory device. A semiconductor wafer is processed for...
US-9,530,487 Method of writing memory with regulated ground nodes
A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first...
US-9,530,486 Adaptive technique for adjusting signal development across bit lines for read operation robustness in memory...
In one embodiment, a memory array has a pair of bit lines for each column of 1-bit SRAM cells and a word line for each row of cells, where, during a memory read...
US-9,530,485 Semiconductor integrated circuit device with reduced leakage current
The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is...
US-9,530,484 Semiconductor apparatus and semiconductor system including the same
A semiconductor apparatus includes a plurality of unit memory blocks and a plurality of sense amplifier arrays configured to be shared with two or more unit...
US-9,530,483 System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory...
A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field...
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