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Patent # Description
US-9,529,675 Data recovery method, data recovery device and distributed storage system
A data recovery method, a data recovery device and a distributed storage system are provided, where the method includes: in a case that a distributed storage...
US-9,529,674 Storage device management of unrecoverable logical block addresses for RAID data regeneration
A host processing system includes a processor, a RAID controller, and a data storage device coupled to the RAID controller and operable to detect first...
US-9,529,673 Memory device having adjustable refresh period and method of operating the same
A memory device includes a plurality of rows of memory cells, a refresh period determination unit, and a refresh control unit. The plurality of rows of memory...
US-9,529,672 ECC word configuration for system-level ECC compatibility
A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one...
US-9,529,671 Error detection in stored data values
An apparatus has a plurality of storage units. A parity generator is configured to generate a parity value in dependence on the respective values stored in the...
US-9,529,670 Storage element polymorphism to reduce performance degradation during error recovery
A data storage system includes a plurality of storage devices forming a storage array for storing data and associated error correction codes and a controller...
US-9,529,669 Error detection and correction in binary content addressable memory (BCAM)
A binary content addressable memory (BCAM) is disclosed. The BCAM includes a memory array, data signature circuitry, and a data match module and compare...
US-9,529,668 Method and system for using NAND page buffers to improve the transfer buffer utilization of a solid state drive
A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower...
US-9,529,667 DRAM error correction event notification
A method in a memory device implementing error correction includes setting an error correction event register to a first value; accessing a memory location in...
US-9,529,666 Decoding method, memory storage device and memory controlling circuit unit
A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence...
US-9,529,665 Double consecutive error correction
Double consecutive error correction is described. An integrated circuit with double consecutive error correction logic includes a data storage structure...
US-9,529,664 Using error correcting codes for parity purposes
Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the...
US-9,529,663 Detection and localization of failures in 3D NAND flash memory
A method includes, in a memory block, which includes at least a string of memory cells that is selectable using at least a select transistor, sensing a current...
US-9,529,662 Dynamic rule-based automatic crash dump analyzer
A method and system for dynamic rule-based automatic crash dump analysis are described. In an example, a dynamic rule-based crash dump analysis system retrieves...
US-9,529,661 Optimal multi-core health monitor architecture
A multi-core processor system and a method of operating the system allocates fault queues in a shared system memory for each virtual machine of a partitioned...
US-9,529,660 Apparatus and method for detecting single flip-error in a complementary resistive memory
Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory...
US-9,529,659 Fault detection apparatus, a fault detection method and a program recording medium
A fault detection apparatus includes a storage unit which stores correlation destruction set information which includes one or more correlations between...
US-9,529,658 Techniques for generating diagnostic identifiers to trace request messages and identifying related diagnostic...
Techniques are described for determining diagnostic information (e.g., a diagnostic identifier) for one or more requests in a cloud computer system. A...
US-9,529,657 Techniques for generating diagnostic identifiers to trace events and identifying related diagnostic information
Techniques are described for determining diagnostic information (e.g., a diagnostic identifier) for one or more events related to operations performed in a...
US-9,529,656 Computer recovery method, computer system, and storage medium
A computer recovery method for a computer system, the computer system having: a management computer having a processor and a memory; and a computer having a...
US-9,529,655 Determining alert criteria in a network environment
Alert conditions datasets are created from historic data taken from actual incidents for which the alert condition datasets are to indicate during future...
US-9,529,654 Recoverable and fault-tolerant CPU core and control method thereof
A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and...
US-9,529,653 Processor register error correction management
Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive...
US-9,529,652 Triaging computing systems
Methods and systems are provided for automatically triaging a server cluster of the type including a plurality of linked servers each running a plurality of...
US-9,529,651 Apparatus and method for executing agent
Methods for processing a one-directional message transmitted by a currently running agent for an agent transaction context (ATC) are presented, the ATC...
US-9,529,650 Method and apparatus for accessing hardware resource
A method and an apparatus for accessing a hardware resource are provided. The method includes configuring permission for one or more privileged instructions...
US-9,529,649 Techniques to compute attribute relationships utilizing a leveling operation in a computing environment
Various embodiments include a system having interfaces, storage devices, memory, and processing circuitry. The system may be coupled with one or more storage...
US-9,529,648 Generic declaration of bindings between events and event handlers regardless of runtime structure
Mechanisms for binding an event handler with an event in association with a component of a hierarchical structure are provided. The mechanisms receive a...
US-9,529,647 System and method for controlling the sale and manufacture of equipment and the transition therebetween
A software and implementable system which provides bi-directional communication between engineering, through software add-ins, and other applications within an...
US-9,529,646 Power-efficient interaction between multiple processors
A technique for processing instructions in an electronic system is provided. In one embodiment, a processor of the electronic system may submit a unit of work...
US-9,529,645 Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of...
Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes intercepting a processor request to apply the lock on...
US-9,529,644 Increasing the efficiency of scheduled and unscheduled computing tasks
One or more processors determine that a user is attempting to execute an unscheduled computing task and estimate the time for execution. One or more processors...
US-9,529,643 Method and system for accelerating task control flow
A computing device (e.g., a mobile computing device, etc.) may be configured to may be configured to better exploit the concurrency and parallelism enabled by...
US-9,529,642 Power budget allocation in a cluster infrastructure
A system and method for allocating power resources among host computers in a cluster uses lower and upper bounds with respect to a power budget to be...
US-9,529,641 Data center thermal model
A system for managing a data center including a plurality of electronic components, each of which are configured to generate varying levels of heat loads under...
US-9,529,640 Work request processor
A network processor includes a schedule, sync and order (SSO) module for scheduling and assigning work to multiple processors. The SSO includes an on-deck unit...
US-9,529,639 System and method for staging in a cloud environment
A method and system for staging in a cloud environment defines a default stage for integration flows. An integration flow is defined by (a) stages including (i)...
US-9,529,638 Resource allocation for virtual machines and logical partitions
A computer determines that a utilization level of a resource has satisfied a threshold. The computer scales the allocation of the resource to the furthest of...
US-9,529,637 Automated scaling of applications in virtual data centers
A system and method for autoscaling a multi-tier application, that has components executing on a plurality of tiers of a virtual data center, allocates...
US-9,529,636 System and method for adjusting guest memory allocation based on memory pressure in virtual NUMA nodes of a...
Techniques for effectuating a virtual Non-Uniform Memory Architecture (NUMA) for virtual machines and adjusting memory in virtual NUMA nodes are described. The...
US-9,529,635 Systems and methods for configuring and launching automated services to a remote device
Systems and methods of the present solution provide for the delivery of automated services via configurable packages that are selectable on a user interface by...
US-9,529,634 Triggered queue transformation
Methods and systems disclosed herein relate generally to evaluating resource loads to determine when to transform queues and to specific techniques for...
US-9,529,633 Variable timeslices for processing latency-dependent workloads
A virtualization host may implement variable timeslices for processing latency dependent workloads. Multiple virtual compute instances on a virtualization host...
US-9,529,632 Interlocked increment memory allocation and access
A method of allocating a memory to a plurality of concurrent threads is presented. The method includes dynamically determining writer threads each having at...
US-9,529,631 Automatic task execution on mobile devices
Embodiments of the disclosure relate to automatic task execution on a mobile device. Aspects include identifying, by a processor, one or more hardware resources...
US-9,529,630 Cloud computing platform architecture
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating recipes having platform-independent,...
US-9,529,629 Computing resource inventory system
Systems and methods of managing computing resources of a computing system are described. A computing resource list and computing resource information may be...
US-9,529,628 Binary editing of applications executed by virtual machines
Systems and techniques are described for modifying an executable file of an application and executing the application using the modified executable file. A...
US-9,529,627 Managing multiple systems in a computer device
Resources of multiple systems are managed in a computer device. A first processing system having a set of dedicated resources also has a resource manager to...
US-9,529,626 Facilitating equitable distribution of thread resources for job types associated with tenants in a multi-tenant...
In accordance with embodiments, there are provided mechanisms and methods for facilitating a fair allocation and usage of thread resources for user messages...
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