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Patent # Description
US-9,537,028 Pinned photodiode (PPD) pixel architecture with separate avalanche region
Described herein is a pinned photodiode pixel architecture having a p-type substrate that is independently biased with respect to a pixel area to provide an...
US-9,537,027 Backside configured surface plasmonic structure for infrared photodetector and imaging focal plane array...
The invention relates to quantum dot and photodetector technology, and more particularly, to quantum dot infrared photodetectors (QDIPs) and focal plane array....
US-9,537,026 Method for manufacturing solar-power-generator substrate and apparatus for manufacturing solar-power-generator...
A method for manufacturing a solar-power-generator substrate by cutting out a semiconductor substrate by slicing a semiconductor ingot and then by forming a...
US-9,537,025 Texturing a layer in an optoelectronic device for improved angle randomization of light
Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for...
US-9,537,024 Metal-dielectric hybrid surfaces as integrated optoelectronic interfaces
An optoelectronic device has a hybrid metal-dielectric optoelectronic interface including an array of nanoscale dielectric resonant elements (e.g.,...
US-9,537,023 Image pickup apparatus and image pickup apparatus manufacturing method
An image pickup apparatus includes: an image pickup device disposed in a first principal surface of a silicon substrate, the image pickup device sensing...
US-9,537,022 Wavelength converting material
A wavelength converting material comprising a phosphate compound have a chemical formula of AB.sub.1-m-nPO.sub.4:M.sub.m, N.sub.n, wherein A comprises an alkali...
US-9,537,021 Photovoltaic cell
A concentrated photovoltaic cell comprises a semiconductor stack comprising an upper surface and a lower surface opposite to the upper surface, wherein the...
US-9,537,020 Solar cell electrode
A method of manufacturing a solar cell electrode comprising steps of: preparing a semiconductor substrate, applying a conductive paste onto the light receiving...
US-9,537,019 Semiconductor device
A semiconductor device includes a base, a semiconductor element disposed on the base, a resist layer formed on the base, and a resin-sealed portion covering the...
US-9,537,018 Photovoltaic cell
A photo-voltaic cell has a first and second two-dimensional array of contact points on the first surface, each coupled to a respective one of base and emitter...
US-9,537,017 Process for forming a planar diode using one mask
A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of...
US-9,537,016 Memory device, gate stack and method for manufacturing the same
A memory device is disclosed. The memory device includes a substrate, including a substrate, including a source region and a drain region; and a gate stack,...
US-9,537,015 Localized fin width scaling using a hydrogen anneal
Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source...
US-9,537,014 Semiconductor device, method for manufacturing semiconductor device, and electronic device
Threshold voltage adjustment method of a semiconductor device is provided. In a semiconductor device in which at least one of transistors included in an...
US-9,537,013 Display device including tapered substrate
A display device is provided including a first substrate comprising a resin material provided with a plurality region provided with a plurality of pixels...
US-9,537,012 Semiconductor device with oxide semiconductor layer
It is an object to manufacture a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. An insulating...
US-9,537,011 Partially dielectric isolated fin-shaped field effect transistor (FinFET)
One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the...
US-9,537,010 Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the...
US-9,537,009 Semiconductor devices including a stressor in a recess and methods of forming the same
Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast...
US-9,537,008 Source/drain structure of semiconductor device
The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises an isolation structure comprising a top surface...
US-9,537,007 FinFET with cut gate stressor
A semiconductor fin includes a channel region. A gate-stressor member, formed of a metal, extends transverse to the fin and includes gate surfaces that straddle...
US-9,537,006 Circuit element including a layer of a stress-creating material providing a variable stress
An integrated circuit includes a first transistor having a first source region, a first drain region, a first channel region, a first gate electrode, and a...
US-9,537,005 Semiconductor device, method of manufacturing semiconductor device, and antenna switch module
Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor...
US-9,537,004 Source/drain formation and structure
A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and...
US-9,537,003 Semiconductor device with charge compensation
A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first...
US-9,537,002 Semiconductor device with SiC base layer
A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed...
US-9,537,001 Reduction of degradation due to hot carrier injection
In a general aspect, a high-voltage metal-oxide-semiconductor (HVMOS) device can include comprising a first gate dielectric layer disposed on a channel region...
US-9,537,000 Semiconductor device with increased safe operating area
A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and...
US-9,536,999 Semiconductor device with control structure including buried portions and method of manufacturing
A semiconductor device includes transistor cells with source zones of a first conductivity type and body zones of a second conductivity type. The source and...
US-9,536,998 Semiconductor device and semiconductor device manufacturing method
[Problem] To provide a semiconductor device wherein withstand voltage of a gate insulating film at the upper edge of a trench is improved, and a method for...
US-9,536,997 Semiconductor device
A semiconductor device includes a semiconductor layer of a first conductivity type, a plurality of first regions that are spaced apart from each other along a...
US-9,536,996 Apparatus and method of manufacturing a support layer
Teaching disclosed herein is an apparatus comprising a support layer. The support layer may be adapted for supporting a heat generator, wherein the support...
US-9,536,994 Method for manufacturing semiconductor device and semiconductor device
A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a...
US-9,536,993 Thin film transistor and method for manufacturing thin film transistor
A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate...
US-9,536,992 Semiconductor structure including a ferroelectric transistor and method for the formation thereof
A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon...
US-9,536,991 Single diffusion break structure
A method of forming a single diffusion break includes patterning a fin hardmask disposed over a substrate. First and second fin arrays separated by an isolation...
US-9,536,990 Methods of forming replacement fins for a FinFET device using a targeted thickness for the patterned fin etch mask
One method disclosed herein includes, among other things, forming a patterned fin having a thickness that is equal to or greater than a target final fin height...
US-9,536,989 Field-effect transistors with source/drain regions of reduced topography
Device structures and fabrication methods for a fin-type field-effect transistor. A first fin and a second fin are formed that are comprised of a semiconductor...
US-9,536,988 Parasitic capacitance reduction
A method of making a semiconductor device includes forming a gate on a substrate; removing an end portion of the gate to form a recess at an end of the gate;...
US-9,536,987 Line-end cutting method for fin structures of FinFETs formed by double patterning technology
A line-end cutting method for fin structures of FinFETs formed by double patterning technology firstly utilizes the SiN hard mask lines to form fin structures...
US-9,536,986 Enriched, high mobility strained fin having bottom dielectric isolation
Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further...
US-9,536,985 Epitaxial growth of material on source/drain regions of FinFET structure
A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a...
US-9,536,984 Semiconductor structure with a spacer layer
A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider...
US-9,536,983 Methods of manufacturing semiconductor devices including gate patterns with sidewall spacers and capping...
A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming...
US-9,536,982 Etch stop for airgap protection
A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides...
US-9,536,981 Field effect transistor device spacers
A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack...
US-9,536,980 Gate spacers and methods of forming same
An embodiment device includes a gate stack extending over a semiconductor substrate, a hard mask disposed on a top surface of the gate stack, and a low-k...
US-9,536,979 FinFET with reduced capacitance
A structure including a plurality of fins etched from a semiconductor substrate, a gate electrode above and perpendicular to the plurality of fins, a pair of...
US-9,536,978 Semiconductor device
To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel...
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