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Patent # Description
US-9,536,926 Magnetic tunnel junction based anti-fuses with cascoded transistors
Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel...
US-9,536,925 Injection pillar definition for line MRAM by a self-aligned sidewall transfer
A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a...
US-9,536,924 Light-emitting diode and application therefor
A light-emitting diode is provided to include: a transparent substrate having a first surface, a second surface, and a side surface; a first conductive...
US-9,536,923 Solid-state image pickup device and image pickup system
A solid-state image pickup device has an image pickup pixel including a first photoelectric conversion portion and a first transistor and a focus detection...
US-9,536,922 Recess with asymmetric walls and method of fabricating the same
A fabricating method of a recess with asymmetric walls includes the steps of providing a substrate comprising a top surface. A recess is formed in the...
US-9,536,921 Radiation image-pickup device and radiation image-pickup display system
A radiation image-pickup device includes: a plurality of pixels each configured to generate signal charge based on radiation; and a field effect transistor used...
US-9,536,920 Stacked image sensor having a barrier layer
An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having ...
US-9,536,919 Solid-state imaging device and method of manufacturing the same, and imaging apparatus
A solid-state imaging device includes: a semiconductor substrate provided with an effective pixel region including a light receiving section that ...
US-9,536,918 Integrated circuit with cavity-based electrical insulation of a photodiode
An integrated circuit includes a semiconductor substrate, at least one photodiode, which is formed on a surface of the semiconductor substrate, at least one...
US-9,536,917 Two color detector leveraging resonant cavity enhancement for performance improvement
Methods and structures for providing single-color or multi-color photo-detectors leveraging cavity resonance for performance benefits. In one example, a...
US-9,536,916 Stacked type image sensor including color separation element and image pickup apparatus including stacked type...
A stacked type image sensor including color separation elements, and an image pickup apparatus including the stacked type image sensor, are provided. The...
US-9,536,915 Image sensor with embedded infrared filter layer
An image sensor includes a substrate, photosensitive devices, a color filter layer, a micro-lens layer and an infrared filter layer. The photosensitive devices...
US-9,536,914 Front side illuminated semiconductor structure with improved light absorption efficiency
There is provided a front side illuminated (FSI) semiconductor structure with improved light absorption efficiency which is configured to provide a reflecting...
US-9,536,913 Display device integrated with touch screen panel and method for fabricating the same
Disclosed is a display device integrated with a touch screen panel and a method for fabricating the same. The display includes: a TFT positioned at each pixel...
US-9,536,912 Method of transferring thin film, method of manufacturing thin film transistor, method of forming pixel...
A method of transferring a thin film is a method of transferring a thin film formed on a first substrate to a second substrate, the method including: allowing...
US-9,536,911 Assembling method for array substrate and color filter substrate of liquid crystal display
The present invention discloses an assembling method for array substrate and color filter substrate of liquid crystal display, which comprises: coating a seal...
US-9,536,910 Transistor substrate and display device
In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied...
US-9,536,909 Display panel with large aperture ratio of pixels
A display panel is provided. A display panel includes a plurality of pixels and a plurality of gate lines. The pixels include a first pixel, a second pixel and...
US-9,536,908 Thin film transistor array panel
A thin-film transistor array panel includes an insulation substrate, a gate line disposed on the insulation substrate, a gate insulating layer disposed on the...
US-9,536,907 Thin film semiconductor device
According to one embodiment, provided is a thin film transistor with which it is possible to reduce the leakage current and thereby, for a liquid crystal...
US-9,536,906 Pixel structure, liquid crystal display array substrate and liquid crystal display panel
A pixel structure is disclosed. The pixel structure includes a plurality of data lines arranged in a first direction, and a plurality of gate lines arranged in...
US-9,536,905 Active matrix substrate and display device using same
An active matrix substrate (5) includes mounting terminals (DT) for supplying a signal from a driver, draw-out lines (22) connecting the mounting terminals (DT)...
US-9,536,904 Light-emitting device
A light-emitting device capable of suppressing variation in luminance among pixels is provided. A light-emitting device includes a pixel and first and second...
US-9,536,903 Display device
To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction...
US-9,536,902 Method of fabricating a thin film transistor substrate using a plurality of photo masks and liquid crystal display
A thin film transistor array substrate includes a pixel electrode layout area, a data electrode layout area, a transparent pixel electrode layer formed in the...
US-9,536,901 Method for fabricating a semiconductor device by bonding a layer to a support with curvature
The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature....
US-9,536,900 Forming fins of different semiconductor materials on the same substrate
A method of manufacturing a semiconductor device, by etching a region of an SOI substrate so that only a portion of the original semiconductor is present above...
US-9,536,899 Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for...
A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second...
US-9,536,898 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer...
US-9,536,897 Semiconductor device and method of fabricating the same
A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region,...
US-9,536,896 Non-volatile memory device having a vertical structure and method of fabricating the same
A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the...
US-9,536,895 Methods of fabricating three-dimensional semiconductor devices
A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor...
US-9,536,894 Non-volatile memory device
According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the...
US-9,536,893 Three-dimensional memory and method for manufacturing the same
A three-dimensional (3D) memory and a method for manufacturing the same are disclosed. According to one embodiment, the 3D memory comprises a thin-film...
US-9,536,892 Pillar-shaped semiconductor memory device and method for producing the same
A pillar-shaped semiconductor memory device includes an i-layer substrate, a silicon pillar, a tunnel insulating layer, a data charge storage insulating layer,...
US-9,536,891 Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device having a plurality of unit cells, each of the plurality of unit cells includes a first transistor suitable for having a fixed...
US-9,536,890 Semiconductor transistor and flash memory, and manufacturing method thereof
A flash memory disposed on a substrate is provided. The flash memory includes a semiconductor transistor including stacked gate structures, lightly doped...
US-9,536,889 Split gate memory device, semiconductor device and forming method thereof
A split gate memory device, a semiconductor device and a manufacturing method thereof are provided. In the split gate memory device, an erasing gate is further...
US-9,536,888 Method to prevent oxide damage and residue contamination for memory device
The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over...
US-9,536,887 Airgap structure and method of manufacturing thereof
A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a...
US-9,536,886 CMOS compatible resonant interband tunneling cell
A semiconductor device includes a first diode connected transistor of a first conductivity type and a second diode connected transistor of a second conductivity...
US-9,536,885 Hybrid FINFET/nanowire SRAM cell using selective germanium condensation
A semiconductor device including a pFET and an nFET where: (i) the gate and conductor channel of the pFET are electrically insulated from a buried oxide layer;...
US-9,536,884 Semiconductor device having positive fixed charge containing layer
A semiconductor device can include a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second...
US-9,536,883 Dual anti-fuse
According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable...
US-9,536,882 Field-isolated bulk FinFET
Disclosed are isolation techniques for bulk FinFETs. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor...
US-9,536,881 Semiconductor devices having fin shaped channels
Semiconductor devices are provided. The semiconductor devices include a first fin; a first gate electrode intersecting the first fin; a first elevated source...
US-9,536,880 Devices having multiple threshold voltages and method of fabricating such devices
Methods of fabricating devices (e.g., FDSOI devices) having multiple threshold voltages are described. One method includes providing a first fixed charge region...
US-9,536,879 FinFET with constrained source-drain epitaxial region
A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the...
US-9,536,878 Semiconductor devices and fabricating methods thereof
Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an...
US-9,536,877 Methods of forming different spacer structures on integrated circuit products having differing gate pitch...
One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being...
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