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Patent # Description
US-9,536,876 Temperature detector and controlling heat
A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar...
US-9,536,875 Semiconductor device
An IGBT is disposed in an IGBT portion, and an FWD is disposed in an FWD portion. A p-type base region and an n.sup.--type drift region are alternately exposed...
US-9,536,874 Method of operating an integrated switchable capacitive device
A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced...
US-9,536,873 Semiconductor device and method of manufacturing the same
Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode...
US-9,536,872 Shallow trench isolation area having buried capacitor
A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow...
US-9,536,871 Integrated switch devices
Various aspects of the technology include an integrated circuit device comprising a compound semiconductor layer and a plurality of input, switch, and ground...
US-9,536,870 SCR with fin body regions for ESD protection
An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled...
US-9,536,869 Electrostatic discharge protection apparatus and method therefor
An electrostatic discharge protection apparatus comprises a stack arrangement having a first electrostatic discharge protection element and a second...
US-9,536,868 Semiconductor device
A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on...
US-9,536,867 N/P boundary effect reduction for metal gate transistors
The present disclosure provides a semiconductor device. A first active region is formed in a substrate. The first active region is elongated in a first...
US-9,536,865 Interconnection joints having variable volumes in package structures and methods of formation thereof
An embodiment method includes analyzing warpage characteristics of a first package component and a second package component and forming a plurality of solder...
US-9,536,864 Package structure and its fabrication method
This disclosure provides a package structure and its fabrication method. The package structure includes: a protective insulation layer; a wiring layer including...
US-9,536,863 Interconnection of a packaged chip to a die in a package utilizing on-package input/output interfaces
Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits...
US-9,536,862 Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass...
US-9,536,861 Semiconductor package including a plurality of stacked chips
A semiconductor package may include a substrate having a first surface and a second surface facing away from the first surface, a window defined through a...
US-9,536,860 Stretchable display
A stretchable display is disclosed. In one aspect, the stretchable display includes a plurality of pixel substrates arranged in a matrix having row and column...
US-9,536,859 Semiconductor device packaging having plurality of wires bonding to a leadframe
A semiconductor device includes a semiconductor element, a lead, and a wire including a first bonding portion bonded to the semiconductor element and a second...
US-9,536,858 Semiconductor device and manufacturing method thereof
Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the...
US-9,536,857 Heating header of semiconductor mounting apparatus and bonding method for semiconductor
A heating header of a semiconductor mounting apparatus includes: a first material; and a second material, the second material being bonded to the first material...
US-9,536,856 Flip chip bonder and flip chip bonding method
Provided is a flip chip bonder including: a pickup flipping collet configured to flip a chip; and a bonding tool configured to receive the chip flipped with the...
US-9,536,855 Semiconductor device and method of fabricating same
A semiconductor device includes, an alloy layer sandwiched between a first Ag layer formed on a mounting board or circuit board and a second Ag layer formed on...
US-9,536,854 Bonding wire for semiconductor device use and method of production of same
Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center...
US-9,536,853 Semiconductor device including built-in crack-arresting film structure
According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding...
US-9,536,852 Lead frame having a perimeter recess within periphery of component terminal
Embodiments described herein relate to a packaged circuit including a lead frame having at least one recess pattern on an internal surface thereof. The at least...
US-9,536,851 Preform structure for soldering a semiconductor chip arrangement, a method for forming a preform structure for...
A preform structure for soldering a semiconductor chip arrangement includes a carbon fiber composite sheet and a solder layer formed over the carbon fiber...
US-9,536,850 Package having substrate with embedded metal trace overlapped by landing pad
A package and method of making the package are provided. An embodiment package includes an integrated circuit supporting a conductive pillar, a substrate having...
US-9,536,849 Semiconductor device and manufacturing method of the same
A semiconductor device includes a semiconductor substrate, a pad electrode formed on the semiconductor substrate, a post electrode formed on the pad electrode...
US-9,536,848 Bond pad structure for low temperature flip chip bonding
Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on...
US-9,536,847 Bump pad structure
An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate...
US-9,536,846 Semiconductor devices having through electrodes, methods of fabricating the same, electronic systems including...
A semiconductor device includes a chip body having an uneven surface including at least two regions at different levels from one another, a through electrode...
US-9,536,845 Device for radiofrequency (RF) transmission with an integrated electromagnetic wave reflector
RF transmission device including at least: a substrate comprising first and second faces opposite to each other; a first RF transmission electronic circuit...
US-9,536,844 Transient antennas and transient electronics
The disclosed antenna structures and electronic microsystems are capable of physically disappearing in a controlled, triggerable manner. Some variations provide...
US-9,536,843 Semiconductor package and semiconductor module
According to one embodiment, a semiconductor package includes: a first metal body on which a part of a waveguide structure is formed; a second metal body...
US-9,536,842 Structure with air gap crack stop
An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a...
US-9,536,841 Semiconductor package with conformal EM shielding structure and manufacturing method of same
A semiconductor package includes a substrate having a front side, a bottom side, and a sidewall along a perimeter of the substrate, a plurality of solder pads...
US-9,536,840 Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield is disclosed. In certain embodiments, at least a graphene layer is positioned between...
US-9,536,839 Semiconductor device and a method of manufacturing the same
To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark....
US-9,536,838 Single crystal ingot, semiconductor wafer and method of manufacturing semiconductor wafers
An embodiment of a method of manufacturing semiconductor wafers comprises forming a notch or a flat in a semiconductor ingot extending along an axial direction....
US-9,536,837 TSV via provided with a stress release structure and its fabrication method
A TSV via structure comprising an upper part made on the side of the front face of a substrate in which electronic components are located and a lower part with...
US-9,536,836 MIS (Metal-Insulator-Semiconductor) contact structures for semiconductor devices
An MIS contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of contact...
US-9,536,835 Semiconductor device and method of manufacturing the same
A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions...
US-9,536,834 Reverse damascene process
The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding...
US-9,536,833 Semiconductor device allowing metal layer routing formed directly under metal pad
A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor...
US-9,536,832 Junctionless back end of the line via contact
A method of forming an interconnect structure includes providing a first dielectric layer, patterning a wire opening in a first dielectric layer, lining the...
US-9,536,831 Semiconductor device and method for fabricating the same
A semiconductor device is disclosed. The semiconductor device includes: a substrate having a die region and a scribe line region defined thereon; and a bonding...
US-9,536,830 High performance refractory metal / copper interconnects to eliminate electromigration
An interconnect structure and method of making the same. A preferred interconnect structure has a first interconnect including a first dual damascene via and...
US-9,536,829 Programmable electrical fuse in keep out zone
An method including forming a back end of the line (BEOL) wiring portion directly on top of a semiconductor base portion, the BEOL wiring portion including a...
US-9,536,828 Semiconductor device
On a semiconductor substrate, coils CL5 and CL6 and pads PD5, PD6, and PD7 are formed. The coil CL5 and the coil CL6 are electrically connected in series...
US-9,536,827 Semiconductor structures
The present disclosure relates to a semiconductor structure which includes a first row of diffusion strap having two sections separated by a first distance, a...
US-9,536,826 Fin field effect transistor (finFET) device structure with interconnect structure
A semiconductor device structure is provided. The semiconductor device structure includes a first metal layer formed over a substrate and an interconnect...
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