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Semiconductor device and method for fabricating the same
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate including a first region and a second...
Dual sided circuit for surface mounting
A method of forming an integrated circuit, including providing a first substrate layer having a center piece and two side pieces on opposite sides of the center...
Conductive structures, systems and devices including conductive structures
and related methods
Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the...
Drawn dummy FeCAP, via and metal structures
An integrated circuit containing hydrogen permeable dummy vias configured in a linear or rectangular array and symmetrically positioned over a component in the...
Semiconductor integrated circuit device having protective split at
peripheral area of bonding pad and method of...
In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a...
Power distribution network
An improved power distribution network for an integrated circuit package that reduces the number of power supply pins that are used in the pin array and...
Transparent substrate having nano pattern and method of manufacturing the
Provided are a transparent substrate having a nano pattern, and a method of manufacturing the same, which enables the nano pattern to be easily formed on the...
Semiconductor package and method of forming the same
A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer,...
Electronic devices and methods of manufacturing electronic devices
Disclosed are a foldable and spreadable electronic device and a method of manufacturing the electronic device. The electronic device may include a flexible...
Encapsulated electronic chip device with mounting provision and externally
accessible electric connection structure
An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, at least one electric...
Semiconductor socket with direct selective metalization
A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A conductive structure is...
Die stacking apparatus and method
Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer...
A semiconductor device includes: a semiconductor chip, and a lead frame. The semiconductor chip is mounted over a die pad. Four suspension leads are connected...
Cavity package with pre-molded cavity leadframe
A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming...
Semiconductor die contact structure and method
A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a...
Flat pad structure for integrating complementary metal-oxide-semiconductor
(CMOS) image sensor processes
A pad structure for a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. A semiconductor substrate is arranged over a back end of line...
Combination of TSV and back side wiring in 3D integration
The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for...
Photo pattern method to increase via etching rate
Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid...
Stack package and semiconductor integrated circuit device including a
A stack package may include a first chip, a second chip, a through silicon via (TSV) and an interface circuit unit. The first chip may include a first internal...
Multi-component cooling element
The invention relates to a micro cooling element (1) with a mounting surface (2) for a component to be cooled, in particular a semiconductor component, which...
Power management integrated circuit (PMIC) integration into a processor
A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory...
Method of manufacturing heat conductive sheet
Provided is a method of manufacturing a heat conductive sheet that itself is imparted with stickiness and has reduced heat resistance due to improved adhesion...
Integrated power module with improved isolation and thermal conductivity
An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the...
A semiconductor device includes a semiconductor chip, a resin mold portion sealing a component in which the semiconductor chip is included, and a bonding layer...
Electronic component having encapsulated wiring board and method for
manufacturing the same
An electronic component including a wiring board having interlayer insulation layers and conductive patterns, the wiring board having a first surface and a...
Packaged semiconductor devices and methods of manufacturing
In one general aspect, a package can include a semiconductor die having a first terminal on a first side of the semiconductor die and a second terminal on a...
Hot-melt type curable silicone composition for compression molding or
The present invention relates to a hot-meltable curable silicone composition for compression molding or laminating and a laminate provided with at least one...
Package structure and the method to fabricate thereof
The invention discloses a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a recess is formed in the...
Substrate treatment apparatus and substrate treatment method
A substrate treatment apparatus includes a processing chamber configured to be capable of storing a substrate; a substrate holder disposed in the processing...
Multiple manufacturing line qualification
Methods and systems for multiple manufacturing line qualification are provided. A method includes establishing a product template and producing products on one...
Multiple threshold voltage trigate devices using 3D condensation
A method of forming a multiple threshold voltage p-channel silicon germanium trigate device using (3D) condensation. The method may include forming a first and...
Techniques for dual dielectric thickness for a nanowire CMOS technology
using oxygen growth
In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are...
Self-aligned gate-first VFETs using a gate spacer recess
Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed. Embodiments include providing a substrate including...
Complementary metal oxide semiconductor field effect transistor, metal
oxide semiconductor field effect...
A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is...
Stable multiple threshold voltage devices on replacement metal gate CMOS
A technique for a multiple voltage threshold transistor structure is provided. A narrow channel and long channel are formed on a fin. An epitaxial layer is...
Semiconductor device with self-heat reducing layers
A semiconductor device comprises a substrate, a source region over the substrate, and a guard ring over the substrate. The guard ring is separated from the...
Fin-double-gated junction field effect transistor
A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a...
Complementary SOI lateral bipolar transistors with backplate bias
A complementary bipolar junction transistor (BJT) integrated structure and methods for fabricating and operating such. The structure includes a monolithic...
Wafer processing method
Disclosed herein is a wafer processing method for dividing a wafer into a plurality of individual devices along a plurality of crossing division lines. The...
Wafer processing method using pulsed laser beam to form shield tunnels
along division lines of a semiconductor...
A wafer is formed with a plurality of division lines on a front surface of a single crystal substrate having an off angle and formed with devices in a plurality...
Method of manufacturing through silicon via stacked structure
A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of...
Integrated circuit (IC) chips with through silicon vias (TSV) and method
of forming the IC
A method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of...
Wafer-level die attach metallization
Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and...
Tungsten film forming method, semiconductor device manufacturing method,
and storage medium
A tungsten film forming method includes: supplying a tungsten chloride gas as a source material of tungsten and a reducing gas towards a substrate to be...
Method of making integrated circuit
Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is...
Method and apparatus for single chamber treatment
The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many...
Selective local metal cap layer formation for improved electromigration
A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and...
Self-aligned double patterning process for metal routing
Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask...
Interconnect apparatus and method
A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard...
Method of manufacturing semiconductor device
An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming...