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Patent # Description
US-9,536,775 Aspect ratio for semiconductor on insulator
A method comprises forming one or more fins in a first region on an insulated substrate. The method also comprises forming one or more fins formed in a second...
US-9,536,774 SOI substrate, method for manufacturing the same, and semiconductor device
An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass...
US-9,536,773 Mechanism of forming a trench structure
Embodiments of a mechanism for forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer are provided. The mechanism involves...
US-9,536,772 Fin structure of semiconductor device
The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding...
US-9,536,771 Gap fill self planarization on post EPI
The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of...
US-9,536,770 Method and apparatus for liquid treatment of wafer shaped articles
An apparatus for processing wafer-shaped articles includes a rotary chuck adapted to hold a wafer shaped article thereon. The rotary chuck includes a peripheral...
US-9,536,769 Pixelated capacitance controlled ESC
Implementations described herein provide a chucking circuit for a pixilated electrostatic chuck which enables both lateral and azimuthal tuning of the RF...
US-9,536,768 Electrostatic carrier for thin substrate handling
Embodiments provided herein generally relate to an electrostatic chuck (ESC). The ESC may comprise a reduced number of stress initiation points, such as holes...
US-9,536,767 Material handling method
The present disclosure relates to a material handling method of performing by means of an automatic mechanical material handling equipment controlled by a...
US-9,536,766 Article transport carriage
An article transport carriage includes a carriage main body configured to travel along a travel path, a support portion configured to support a bottom surface...
US-9,536,765 Load port unit and EFEM system
A load port unit can prevent or control leakage of inert gas from an EFEM system to the outside. The load port unit used in the EFEM system is provided with an...
US-9,536,764 End effector for wafer transfer system and method of transferring wafers
An end effector of a wafer transfer system includes synchronously movable blades operable to hold and release wafers. The end effector comprises an end effector...
US-9,536,763 Semiconductor stocker systems and methods
In an embodiment, the present invention discloses cleaned storage processes and systems for high level cleanliness articles, such as extreme ultraviolet (EUV)...
US-9,536,762 Method and apparatus for thermal mapping and thermal process control
A thermal processing apparatus is provided in accordance with some embodiments. The thermal processing apparatus includes a heating source for transmitting...
US-9,536,761 Substrate liquid processing apparatus
A substrate liquid processing apparatus includes a cup 50 configured to receive a processing liquid supplied onto a substrate. The cup includes a ring-shaped...
US-9,536,760 Semiconductor die encapsulation or carrier-mounting method, and corresponding semiconductor die encapsulation...
A semiconductor die encapsulation or carrier-mounting method and apparatus for manufacturing a semiconductor product, wherein a first tool part for holding...
US-9,536,759 Baking apparatus and method
A baking apparatus for baking a wafer is provided. The baking apparatus includes a wafer chuck configured to hold the wafer, and a heating device disposed over...
US-9,536,758 Time-varying frequency powered semiconductor substrate heat source
A semiconductor substrate can include two or more electrodes, located directly or indirectly on the semiconductor substrate, separated from each other and...
US-9,536,757 Device manufacturing cleaning process using vaporized solvent
A cleaning method using vaporized solvent is provided. A solvent-containing vapor is generated, wherein the solvent-containing vapor comprises a solvent. The...
US-9,536,756 Semiconductor packages separated using a sacrificial material
One or more embodiments are directed to semiconductor packages that are assembled using a sacrificial material, that when removed, separates the assembled...
US-9,536,755 Laminating system
It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it...
US-9,536,754 Method of forming contact structure of gate structure
A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first...
US-9,536,753 Circuit substrate interconnect
A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the...
US-9,536,752 Slurry for chemical mechanical polishing and polishing method for substrate using same
The present invention provides a slurry for chemical mechanical polishing comprising water-soluble clathrate compound (a), polymer compound (b) having an acidic...
US-9,536,751 Method for forming patterns for semiconductor device
A method for forming patterns for semiconductor device includes following steps. A substrate is provided. The substrate includes a hard mask layer and a...
US-9,536,750 Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme
A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and...
US-9,536,749 Ion energy control by RF pulse shape
A method for slope control of ion energy is described. The method includes receiving a setting indicating that an etch operation is to be performed using a...
US-9,536,748 Use of ion beam etching to generate gate-all-around structure
Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in...
US-9,536,747 Method for treating a gallium nitride layer comprising dislocations
A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its...
US-9,536,746 Recess and epitaxial layer to improve transistor performance
Some embodiments of the present disclosure relate to a semiconductor device configured to mitigate against parasitic coupling while maintaining threshold...
US-9,536,745 Tungsten film forming method
A tungsten film forming method for forming a tungsten film on a surface of a target substrate by an ALD (atomic layer deposition) method comprises adding a...
US-9,536,744 Enabling large feature alignment marks with sidewall image transfer patterning
In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask....
US-9,536,743 Process for manufacturing a power device with a trench-gate structure and corresponding device
An embodiment for realizing a power device with trench-gate structure integrated on a semiconductor substrate, and including etching the semiconductor substrate...
US-9,536,742 Lateral double-diffused MOSFET and fabrication method thereof
The present disclosure provides a method for forming a Lateral Double-Diffused MOSFET (LDMOS). The method includes providing a semiconductor substrate having a...
US-9,536,741 Method for performing activation of dopants in a GaN-base semiconductor layer by successive implantations and...
The method for performing activation of n-type or p-type dopants in a GaN-base semiconductor includes the following steps: providing a substrate including a...
US-9,536,740 Increasing the doping efficiency during proton irradiation
A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the...
US-9,536,739 Self-cut sidewall image transfer process
A plurality of mandrels is formed on a silicon substrate. The mandrels are spaced apart at a given pitch, wherein at least one of the plurality of mandrels is...
US-9,536,738 Vertical gate all around (VGAA) devices and methods of manufacturing the same
Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: forming a first...
US-9,536,737 Nanostructure and process of fabricating same
A process of fabricating a nanostructure is disclosed. The process is effected by growing the nanostructure in situ within a trench formed in a substrate and...
US-9,536,736 Reducing substrate bowing caused by high percentage sige layers
The present invention relates generally to semiconductor devices and more particularly, to a structure and method for reducing substrate bowing resulting from...
US-9,536,735 Method for preparing graphene
A method of preparing graphene includes supplying a gas on a metal catalyst, the gas including CO.sub.2, CH.sub.4, and H.sub.2O, and reacting and cooling the...
US-9,536,734 Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device is disclosed. The method includes forming a film on a substrate by performing a cycle a predetermined number of...
US-9,536,733 Hydrogen-free silicon-based deposited dielectric films for nano device fabrication
Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as ...
US-9,536,732 Low temperature fabrication of lateral thin film varistor
A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do...
US-9,536,731 Wet clean process for removing C.sub.xH.sub.yF.sub.z etch residue
A method for cleaning etch residues that may include treating an etched surface with an aqueous lanthanoid solution, wherein the aqueous lanthanoid solution...
US-9,536,730 Cleaning formulations
A composition and method for removing copper-containing post-etch and/or post-ash residue from patterned microelectronic devices is described. The removal...
US-9,536,729 Tubular light source having overwind
Embodiments of the present invention generally relate to a tubular lamp with a coiled filament having an overwind wrapped around the coil. In one embodiment,...
US-9,536,728 Lamp for rapid thermal processing chamber
A lamp assembly for the lamp assembly adapted for use in a substrate thermal processing chamber to heat the substrate to temperatures up to at least about...
US-9,536,727 Time-of-flight mass spectrometer and method of controlling same
A flight-of-time mass spectrometer is offered which can provide a variable range of collisional energies that can be made wider than heretofore. Also, a method...
US-9,536,726 MALDI-TOF mass spectrometers with delay time variations and related methods
MALDI-TOF MS systems have solid state lasers and successive and varied delay times between ionization and acceleration (e.g. extraction) to change focus masses...
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