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Circuitry and method for critical path timing speculation in RAMs
User data or constantly toggling functional critical path timing sensors measure delays in actual critical paths that include a RAM. Variable resistors or...
Data transfer circuit
A data transfer circuit has a first data transmission unit and two or more second shift registers. The first data transmission unit has a first shift register...
Gate drive circuit and shift register
The present invention discloses a gate drive circuit and a shift register. The gate drive circuit comprises a plurality of shift register circuits which are...
Programming of antifuse cells
For programming an antifuse memory, the power consumption of the memory is assessed during programming mode. The power consumption is compared with a threshold....
A nonvolatile memory includes a memory area including plural first magnetoresistive elements each serving as a memory element, each first magnetoresistive...
Method and system for improving the radiation tolerance of floating gate
A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block...
Hybrid-HDD with improved data retention
Data are refreshed in a nonvolatile solid-state device to significantly reduce the likelihood of data retention errors. Test data are written in a region of the...
Apparatuses and methods to control body potential in memory operations
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line...
Ad hoc digital multi-die polling for peak ICC management
Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases,...
Non-volatile memory device and method for reading out data
A non-volatile memory device includes a first electrode layer, a second electrode layer adjacent to the first electrode layer, a third electrode layer adjacent...
Nonvolatile semiconductor memory device and control method thereof
A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and...
Common source architecture for split gate memory
A memory system has an array of split gate non-volatile NVM cells that are in program sectors and the program sectors make up one or more erase sectors. The...
Semiconductor memory device including a 3-dimensional memory cell array
and a method of operating the same
A semiconductor memory device may include a plurality of cell strings. Each of the cell strings may include at least one source selection transistor connected...
Digital signaling processing for three dimensional flash memory arrays
A method for multilevel programming flash memory cells of a three dimensional array of flash memory cells, the method may include receiving or determining a...
3D NAND memory using two separate SSL structures in an interlaced
configuration for one bit line
A semiconductor device includes a plurality of active strips, where active strips in the plurality are coupled together at one end by a pad and terminated at...
Semiconductor integrated circuit adapted to output pass/fail results of
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit...
Memory modules with multi-chip packaged integrated circuits having flash
A memory module is provided. In one example, the memory module includes a printed circuit board with one or more connectors, and a plurality of multi-chip...
Content addressable memory device
Disclosed aspects include a content addressable memory device comprising at least two memory banks connectable to a global search line. Each memory bank...
Preservation circuit and methods to maintain values representing data in
one or more layers of memory
Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array...
Seasoning phase change memories
A seasoned phase change memory has been subjected to a longer pulse to adjust resistance levels prior to use of the phase change memory.
Resistive memory device and operating method
Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device...
Impedance matching system for DDR memory
A memory system is deigned for impedance matching using a network of resistors that are tuned to reduce reflections on a shared bus. Any deviation from the...
Methods and apparatuses for determining threshold voltage shift
Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells...
Method for writing data into flash memory and related control apparatus
A method for writing data into a flash memory, wherein the flash memory includes a plurality multi-level cells, and each of the plurality of multi-level cells...
Threshold voltage grouping of memory cells in same threshold voltage range
A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present...
Simultaneous multi-page commands for non-volatile memories
Mechanisms are provided, in a non-volatile memory device comprising a non-volatile memory and a memory controller, for controlling an operation of the...
Optoelectronic device, in particular memory device
A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second...
Among other things, techniques and systems are provided for activating a memory cell of a memory arrangement in preparation for at least one of a read operation...
Low-power SRAM cells
The present invention provides a memory unit (4) comprising: a storage element (6) comprising a pair of back to back inverters (12a, 12b and 14a, 14b) having...
Three-port bit cell having increased width
An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read...
Systems and methods for reducing standby power in floating body memory
Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters...
Data reception chip
A data reception chip coupled to an external memory including a first input-output pin to output first data and including a comparison module, a voltage...
Low power receiver with wide input voltage range
An input receiver is provided with a pass transistor that is controlled to pass an input signal to an inverter only while a first binary state for the input...
Memory device and semiconductor device
A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit...
Staggered DLL clocking on N-Detect QED to minimize clock command and delay
Apparatuses and methods are described for meeting timing and latency requirements using staggered clocking within the command path. In one example, an apparatus...
System and method of memory electrical repair
Aspects of the disclosure provide an integrated circuit (IC) chip having a memory controller. The memory controller includes a memory interface circuit...
Low-power source-synchronous signaling
A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel...
Reduction of power consumption in memory devices during refresh modes
Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging...
Semiconductor devices and integrated circuits including the same
A first semiconductor device equalizes levels of a bit line and a complementary bit line of a high-order bit line pair in a first memory block using a first...
Memory device and memory system having the same
A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a...
SRAM storage unit based on DICE structure
The present invention provides an improved SRAM memory cell based on a DICE structure, which comprises following structures: four inverter structures formed...
Nonvolatile logic gate device
A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are...
Magnetic memory, spin element, and spin MOS transistor
A magnetic memory according to an embodiment includes: a multilayer structure including a semiconductor layer and a first ferromagnetic layer; a first wiring...
Enable/disable of memory chunks during memory access
Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed...
Tamper-resistant non-volatile memory device
A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value...
Clock signal processor and non-volatile memory device including the same
A clock signal processor includes a duty cycle corrector, a switch point calculator, and a multiplexer. The duty cycle corrector generates a second clock signal...
Semiconductor integrated circuit capable of precisely adjusting delay
amount of strobe signal
An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal and receives a data...
Apparatus and method for writing data to memory array circuits
A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first...
Data movement in memory devices
Apparatus, systems, and methods for data movement in a memory device are described. In one embodiment, a memory controller comprises logic to move a row of data...
Semiconductor device with a sense amplifier unit responsive to a voltage
change of input signals and a sense...
A sense amplifier circuit includes an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is...