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Patent # Description
US-9,535,872 Physical chassis as a different number of logical chassis
A system includes a first physical chassis comprising a first chassis management unit ("CMU"). The first CMU is configured to communicate with a second CMU in...
US-9,535,871 Dynamic routing through virtual appliances
A computing device executes a virtual machine that provides a service to a client. The computing device monitors one or more conditions associated with at least...
US-9,535,870 Acknowledgement-less protocol for solid state drive interface
The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a...
US-9,535,869 Method and apparatuses for respectively transferring information within and between system-on-chips (SOCS) via...
A system including a first system-on-chip (SoC) and a second SoC. The first SoC includes a first module and a second module. The second module is separate from...
US-9,535,868 Apparatus and method for network traffic classification and policy enforcement
A machine has a bus, an input port connected to the bus to receive inbound network traffic, an output port connected to the bus to convey outbound network...
US-9,535,867 Method, device, system and storage medium for implementing packet transmission in PCIE switching network
Embodiments of the present invention disclose a peripheral component interconnect express interface control unit. The unit includes a P2P module, configured to...
US-9,535,866 Asymmetric storage device wide link
A wide link communicates information between a storage enclosure having plural storage devices and an information handling system by selectively configuring...
US-9,535,865 Interconnection of multiple chips in a package
An interface. A first set of single-ended transmitter circuits reside on a first die having a master device. A first set of single-ended receiver circuits...
US-9,535,864 Computer system and control method thereof
The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one...
US-9,535,863 System and method for supporting message pre-processing in a distributed data grid cluster
A system and method can support message pre-processing in a distributed data grid. The system can associate a message bus with a service thread on a cluster...
US-9,535,862 System and method for supporting a scalable message bus in a distributed data grid cluster
A system and method can a scalable message bus in a distributed data grid. The system can provide a plurality of message buses in the distributed data grid,...
US-9,535,861 Methods and systems for routing in a state machine
A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a...
US-9,535,860 Arbitrating memory accesses via a shared memory fabric
In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated...
US-9,535,859 Sharing message-signaled interrupts between peripheral component interconnect (PCI) I/O devices
A PCI function, such as a device driver, may request that additional MSI resources be allocated to an I/O device coupled to a PCI Host Bridge (PHB). However,...
US-9,535,858 Signal processing system and associated method
The present invention provides a signal processing system and associated method. The signal processing system includes converter(s) for conversion between...
US-9,535,857 Autonomous device interaction
A method, system, apparatus, and computer program product are provided for facilitating autonomous device interaction. A method is provided that includes...
US-9,535,856 Data access to a storage tier on a client in a multi-tiered storage system
Embodiments of the present disclosure may relate to methods and a computer program product for allowing writes based on a granularity level. The method for a...
US-9,535,855 Reorganization of virtualized computer programs
In an embodiment, a data processing method comprises detecting that a computer is loading a dynamic loader in a user space, the dynamic loader intending to load...
US-9,535,854 Building an undo log for in-memory blocks of data
Provided are techniques for building an undo log for in-memory blocks of data. Permission on a block of data in memory is set to prevent updates to that block...
US-9,535,853 Building an undo log for in-memory blocks of data
Provided are techniques for building an undo log for in-memory blocks of data. Permission on a block of data in memory is set to prevent updates to that block...
US-9,535,852 System and method for secured host-slave communication
Slave device circuitry, including processing circuitry which is configured to determine a new session identification value; determine a seed value using a...
US-9,535,851 Transactional memory that performs a programmable address translation if a DAT bit in a transactional memory...
A transactional memory receives a command, where the command includes an address and a novel DAT (Do Address Translation) bit. If the DAT bit is set and if the...
US-9,535,850 System and method for efficient DMA transfers
A method and apparatus are provided in which a host device and a peripheral device are adapted to perform efficient data transfers. The host receives one or...
US-9,535,849 IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect
An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may...
US-9,535,848 Using cuckoo movement for improved cache coherency
Example implementations of the present disclosure are directed to handling the eviction of a conflicting cuckoo entry while reducing performance degradation...
US-9,535,847 Apparatus and method for compression of configuration data
An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor...
US-9,535,846 Using a decrementer interrupt to start long-running hardware operations before the end of a shared processor...
Systems, methods, and computer program products to perform an operation, the operation comprising processing a first logical partition on a shared processor for...
US-9,535,845 Cache control device and cache control method
A cache control device includes an area determination unit that determines an area of a cache memory which is allocated to each instruction flow on the basis of...
US-9,535,844 Prioritization for cache systems
In a data storage environment, a caching system includes a synchronous I/O module to stage cache promotions, and an asynchronous I/O module to de-stage cache...
US-9,535,843 Managed memory cache with application-layer prefetching
In order to prevent data thrashing and the resulting performance degradation, a computer system may maintain an application-layer cache space to more...
US-9,535,842 System and method for performing message driven prefetching at the network interface
Each computing node of a distributed computing system may implement a hardware mechanism at the network interface for message driven prefetching of application...
US-9,535,841 Cache memory and cache memory control unit
Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a...
US-9,535,840 Parallel destaging with replicated cache pinning
Methods, apparatus and computer program products implement embodiments of the present invention that include identifying non-destaged first data in a write...
US-9,535,839 Arithmetic processing device, method of controlling arithmetic processing device, and information processing device
An arithmetic processing device has a first arithmetic processing unit including a first instruction controller that controls a write instruction to a memory...
US-9,535,838 Atomic operations in PCI express
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is...
US-9,535,837 Decentralized online cache management for digital content conveyed over shared network connections based on...
A first cache is provided to cache a first portion of a first block of digital content received over a network connection shared between a first user associated...
US-9,535,836 Non-volatile memory update tracking
A technique includes performing an update to a location of a non-volatile memory. The update is created by execution of at least one machine executable...
US-9,535,835 Non-volatile cache
A method for managing a storage device including determining whether the storage device includes a non-volatile cache, scanning for a clear cache instruction...
US-9,535,834 Electronic device including memory arrays with variable resistance storage elements arranged on different sides...
An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines;...
US-9,535,833 Reconfigurable processor and method for optimizing configuration memory
A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the...
US-9,535,832 Multi-hierarchy interconnect system and method for cache system
A multi-hierarchy interconnect system for a cache system having a tag memory and a data memory includes an address interconnect scheduling device and a data...
US-9,535,831 Page migration in a 3D stacked hybrid memory
A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture...
US-9,535,830 Fast block device and methodology
A device, memory, method and system directed to fast data storage on a block storage device. New data is written to an empty write block. A location of the new...
US-9,535,829 Non-volatile memory interface
In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a...
US-9,535,828 Leveraging non-volatile memory for persisting data
Data temporarily stored in volatile memory (e.g., RAM) on a host machine can be protected using a component such as an NV-DIMM, which includes components such...
US-9,535,827 RAM disk using non-volatile random access memory
A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS)...
US-9,535,826 Automatic communication and optimization of multi-dimensional arrays for many-core coprocessor using static...
There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes...
US-9,535,825 Information processing device and information processing method
An information processing device includes a memory; and a processor that executes a program stored in the memory, wherein the processor executes an operation...
US-9,535,824 Payload generation for computer software testing
A method of generating test payloads for a target system includes receiving a plurality of reference programs, each reference program modelling at least one...
US-9,535,823 Method and apparatus for detecting software bugs
A computer-implemented method and apparatus for unit testing, the method comprising: intercepting user interactions when a user is testing a function...
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