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Patent # Description
US-9,543,435 Asymmetric multi-gate finFET
An asymmetrical finFET device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The fin extends along a length of the...
US-9,543,434 Device active channel length/width greater than channel length/width
A device including a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is situated over the...
US-9,543,433 Dual work function recessed access device and methods of forming
A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage...
US-9,543,432 High voltage LDMOS device with an increased voltage at source (high side) and a fabricating method thereof
A high voltage LDMOS device having high side source voltage, an n type buried layer and a p type buried layer situated on the interface between a p type...
US-9,543,431 Radio frequency LDMOS device and a fabrication method therefor
A radio frequency LDMOS device, wherein the drift region includes a first injection region and a second injection region; the first injection region situated...
US-9,543,430 Segmented power transistor
A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain...
US-9,543,429 Silicon carbide semiconductor device
There is provided a silicon carbide semiconductor device allowing for increased switching speed with a simpler configuration. A silicon carbide semiconductor...
US-9,543,428 Silicon carbide semiconductor device and method for producing the same
An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region....
US-9,543,427 Semiconductor device and method for fabricating the same
A semiconductor device includes: semiconductor layer having an impurity region of a first conductivity type; a gate insulating layer, at least a part of the...
US-9,543,426 Semiconductor devices with self-aligned contacts and low-k spacers
One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a...
US-9,543,425 Multi-finger large periphery AlInN/AlN/GaN metal-oxide-semiconductor heterostructure field effect transistors...
MOSHFET devices are provided, along with their methods of fabrication. The MOSHFET device can include a substrate; a multilayer stack on the substrate; a...
US-9,543,424 Method for growing III-V epitaxial layers and semiconductor structure
Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a...
US-9,543,423 Hot-electron transistor having multiple MSM sequences
In one aspect, a transistor comprises a metal emitter, a first semiconductor barrier, a metal base, a second semiconductor barrier, and a metal collector. The...
US-9,543,422 Semiconductor device
A semiconductor device includes a second region of a second conductivity type above a first region of a first conductivity type. A gate electrode has a portion...
US-9,543,421 Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region
A semiconductor device includes a semiconductor layer, a plurality of gate trenches, a gate electrode in the plurality of gate trenches, an n.sup.+-type emitter...
US-9,543,420 Protection device and related fabrication methods
Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor...
US-9,543,419 FinFET structures and methods of forming the same
An embodiment is a method including forming an epitaxial portion over a substrate, the epitaxial portion including a III-V material. A damaged material layer...
US-9,543,418 Semiconductor liner of semiconductor device
The disclosure relates to a fin field effect transistor (FinFET) formed in and on a substrate having a major surface. The FinFET includes a fin structure...
US-9,543,417 High mobility devices and methods of forming same
An embodiment method includes forming a first fin and a second fin over a semiconductor substrate. The first fin includes a first semiconductor strip of a first...
US-9,543,416 Methods of forming products with FinFET semiconductor devices without removing fins in certain areas of the product
One illustrative method disclosed herein includes, among other things, forming a first plurality of fins in the first region of the substrate, a second...
US-9,543,415 Thin film transistor driving backplane and manufacturing method thereof, and display panel
The embodiments of the present invention provide a thin film transistor driving backplane and a manufacturing method thereof, and a display panel. The...
US-9,543,414 Method of forming a silicon-carbide device with a shielded gate
A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface,...
US-9,543,413 Corner layout for high voltage semiconductor devices
A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell...
US-9,543,412 Method for manufacturing silicon carbide semiconductor device
A silicon carbide substrate including a first layer having first conductivity type, a second layer having second conductivity type, and a third layer having the...
US-9,543,411 Lateral double diffusion metal-oxide-semiconductor (LDMOS) transistors and fabrication method thereof
A lateral double diffusion metal-oxide-semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate having a well...
US-9,543,410 Semiconductor device and formation thereof
A semiconductor device and method of forming the same are described. A semiconductor device includes an active area adjacent a gate structure. The gate...
US-9,543,409 Production of spacers at flanks of a transistor gate
The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of...
US-9,543,408 Method of forming patterned hard mask layer
A method of forming a patterned hark mask layer includes the following steps. A semiconductor substrate is provided. An amorphous silicon layer is formed on the...
US-9,543,407 Low-K spacer for RMG finFET formation
A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers...
US-9,543,406 Structure and method for overlay marks
The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the...
US-9,543,405 Method of manufacturing a reduced free-charge carrier lifetime semiconductor structure
A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure includes forming a plurality of transistor gate structures in trenches...
US-9,543,404 Vertical BJT for high density memory
Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled...
US-9,543,403 Bipolar junction transistor with multiple emitter fingers
Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer...
US-9,543,402 Integrated high performance lateral schottky diode
A diode includes a two-dimensional electron gas formed in a heterojunction defined between first and second semiconductor material layers. First and second...
US-9,543,401 3D semiconductor integrated circuit device and method of manufacturing the same
A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and...
US-9,543,400 Ohmic contact to semiconductor
A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the...
US-9,543,399 Device having sloped gate profile and method of manufacture
A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer...
US-9,543,398 Semiconductor switching device including charge storage structure
A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn...
US-9,543,397 Backside source-drain contact for integrated circuit transistor devices and method of making same
An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source...
US-9,543,396 Vertical transistor device structure with cylindrically-shaped regions
A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of cylindrically-shaped dielectric regions...
US-9,543,395 Normally-off power JFET and manufacturing method thereof
In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in...
US-9,543,394 Quantum rod and method of fabricating the same
A quantum rod includes a core of ZnS semiconductor particle having a rod shape; and a transition metal with which the core is doped and which is biased at one...
US-9,543,393 Group III nitride wafer and its production method
The present invention discloses a group III nitride wafer such as GaN, AlN, InN and their alloys having one surface visually distinguishable from the other...
US-9,543,392 Transparent group III metal nitride and method of manufacture
Large-area, low-cost single crystal transparent gallium-containing nitride crystals useful as substrates for fabricating GaN devices for electronic and/or...
US-9,543,391 High electron mobility transistor having reduced threshold voltage variation and method of manufacturing the same
According to example embodiments a transistor includes a channel layer on a substrate, a first channel supply layer on the channel, a depletion layer, a second...
US-9,543,390 Transistor having a heterojunction and manufacturing method thereof
A transistor includes a semiconductor substrate comprising a first region and a second region. The transistor further includes an emitter and a base disposed on...
US-9,543,389 Semiconductor device with recombination region
A semiconductor device includes a drift zone in a semiconductor body. A charge-carrier transfer region forms a pn junction with the drift zone in the...
US-9,543,388 Complementary metal-oxide silicon having silicon and silicon germanium channels
A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first...
US-9,543,387 Semiconductor device and manufacturing method thereof
A semiconductor device includes a gate structure located on a substrate and a raised source/drain region adjacent to the gate structure. The raised source/drain...
US-9,543,386 Semiconductor device with field electrode structures, gate structures and auxiliary diode structures
A semiconductor device includes field electrode structures extending in a direction vertical to a first surface in a semiconductor body. Cell mesas are formed...
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