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Patent # Description
US-9,543,335 Liquid-crystal display and element substrate thereof
An element substrate is provided, including a substrate, a metal layer and a planarization layer. The metal layer is located on the substrate. The metal layer...
US-9,543,334 Display panel
A display panel is provided. The display panel includes a substrate including a non-display region containing a thin film transistor, which includes a...
US-9,543,333 Display apparatus
A display apparatus including a display area on a substrate, the display area including at least a display device; and a non-display area adjacent to the...
US-9,543,332 Array substrate, display panel and display device
An array substrate comprises: a plurality of flexible cushions; and a plurality of signal lines, wherein the signal lines have ends respectively located on the...
US-9,543,331 Array substrate and manufacturing method thereof, display device
An array substrate and manufacturing method thereof, and a display device are capable of preventing light reflection from a drain electrode, and guaranteeing...
US-9,543,330 Method of manufacturing a thin film transistor and a pixel structure
A method manufacturing a thin film transistor is provided. A gate, a first insulation layer covering the gate, a semiconductor layer over the gate, and a first...
US-9,543,329 Thin film transistor substrate and method for manufacturing the same
A thin film transistor substrate includes: a gate insulating film that covers a gate electrode and a common electrode; a transparent oxide film selectively...
US-9,543,328 Metal oxide TFT device and method for manufacturing the same
A method for manufacturing a metal oxide TFT device is provided. The method includes: selecting a substrate and forming a gate electrode on a first side of the...
US-9,543,327 Semiconductor device having insulation layer with concave portion and semiconductor layer that includes channel...
A first insulation layer includes a concave portion. A semiconductor layer includes a source area and a drain area, and a channel area disposed at the concave...
US-9,543,326 Display device
According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second...
US-9,543,325 Array substrate and manufacturing method thereof, liquid crystal display panel and display device
An array substrate and a manufacturing method thereof, a liquid crystal display panel and a display device are provided, the array substrate comprises a base...
US-9,543,324 Array substrate, display device and manufacturing method of the array substrate
An array substrate, a display device and a manufacturing method of the array substrate. The array substrate includes: a base substrate (1) and a plurality of...
US-9,543,323 Strain release in PFET regions
A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric...
US-9,543,322 Methods for producing a thin film ferroelectric device using a two-step temperature process on an organic...
Methods for producing ferroelectric device are described. A method includes positioning an organic polymeric ferroelectric layer between two conductive...
US-9,543,321 Semiconductor memory device and method of manufacturing the same
A semiconductor memory device according to an embodiment comprises a stacked body, a semiconductor layer, a charge accumulation layer, and a slit portion. The...
US-9,543,320 Three-dimensional memory structure having self-aligned drain regions and methods of making thereof
A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying...
US-9,543,319 Vertical channel structure
A vertical channel structure including a substrate, a plurality of stacked structures, a charge storage structure, a channel structure and a dielectric...
US-9,543,318 Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors
An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact...
US-9,543,317 Semiconductor device and method of manufacturing the same
A semiconductor device includes interlayer insulating films spaced apart from each other and stacked over each other, and wherein first ends of the interlayer...
US-9,543,316 Semiconductor memory device and method of fabricating the same
Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a...
US-9,543,315 Semiconductor device
The memory cell includes a gate insulating film, a control gate electrode, a cap insulating film, a cap layer, another gate insulating film, and a memory gate...
US-9,543,314 Manufacturing method of semiconductor device and semiconductor device
A semiconductor device including a memory cell having a control gate electrode and a memory gate electrode formed via a charge accumulation layer with respect...
US-9,543,313 Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the...
US-9,543,312 Method for manufacturing a nonvolatile memory device
A method for manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention may include providing a substrate comprising a...
US-9,543,311 Vertical memory cell with non-self-aligned floating drain-source implant
Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also...
US-9,543,310 Semiconductor storage device having communicated air gaps between adjacent memory cells
A semiconductor storage device according to an embodiment of the invention includes a semiconductor substrate and a plurality of memory cells on the...
US-9,543,309 Antifuse memory cells and arrays thereof
An antifuse memory cell includes an antifuse element and a gate PN diode. The antifuse element includes a gate terminal coupled to a word line, a drain terminal...
US-9,543,308 Semiconductor device
A semiconductor device includes a bit line structure on a substrate, the bit line structure having a polysilicon layer pattern doped with impurities, and a...
US-9,543,307 Vertical memory devices and methods of manufacturing the same
A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold...
US-9,543,306 Sub word line driver of a semiconductor memory device
A sub word line driver of a semiconductor memory device including a sub word line driver is disclosed. The sub word line driver of a semiconductor memory device...
US-9,543,305 Reverse conducting power semiconductor device
A RC power semiconductor is provided which comprises a plurality of diode cells and a plurality of GCT cells. Each GCT cell comprises a first cathode layer with...
US-9,543,304 Vertical junction FinFET device and method for manufacture
A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate...
US-9,543,303 Complementary metal oxide semiconductor device with dual-well and manufacturing method thereof
The present invention discloses a dual-well complementary metal oxide semiconductor (CMOS) device and a manufacturing method thereof. The dual-well CMOS device...
US-9,543,302 Forming IV fins and III-V fins on insulator
A semiconductor structure including: a set of first fins in a pFET region and a set of second fins in an nFET region, the first fins and the second fins are on...
US-9,543,301 Fin-last FinFET and methods of forming same
Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the...
US-9,543,300 CMOS transistor, semiconductor device including the transistor, and semiconductor module including the device
Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include...
US-9,543,299 P-N bimodal conduction resurf LDMOS
RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is...
US-9,543,298 Single diffusion break structure and cuts later method of making
A method of forming a single diffusion break includes etching rows of fins into a substrate of a structure from a patterned fin hardmask, the remaining fin...
US-9,543,297 Fin-FET replacement metal gate structure and method of manufacturing the same
A method of forming fins and the resulting fin-shaped field effect transistors (finFET) are provided. Embodiments include forming silicon (Si) fins over a...
US-9,543,296 ESD clamp with auto biasing under high injection conditions
In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V...
US-9,543,295 Semiconductor device
A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of...
US-9,543,294 Semiconductor device
A semiconductor device includes a semiconductor substrate; and a temperature sense diode fixed on the semiconductor substrate. The temperature sense diode...
US-9,543,293 Power semiconductor device having trench gate type IGBT and diode regions
Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region....
US-9,543,292 Field effect transistor with integrated Zener diode
One or more Zener diodes and a field effect transistor having a drain connected in series with the one or more Zener diodes are integrally formed by a plurality...
US-9,543,291 Method of forming a high electron mobility semiconductor device and structure therefor
In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate...
US-9,543,290 Normally-off junction field-effect transistors and application to complementary circuits
A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a...
US-9,543,289 Manufacturing method of semiconductor device
A manufacturing method of a semiconductor device includes: depositing a thin film semiconductor layer on a semiconductor substrate with an insulating film...
US-9,543,288 Semiconductor isolation structure
The invention relates to a semiconductor isolation structure. More particularly, the present invention relates to a semiconductor isolation structure suitable...
US-9,543,287 Integrated circuit and method for fabricating an integrated circuit equipped with a temperature probe
This integrated circuit comprises: a substrate, a first electrical conductor comprising a first end, the first electrical conductor being electrically...
US-9,543,286 Semiconductor device
A semiconductor device which is capable of operating at an operation frequency "f", includes a substrate, a first element unit and a second element unit. The...
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