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Patent # Description
US-9,543,285 Display panel
A display panel including a plurality of sub-pixel groups arranged repeatedly to form a pixel array. Each of the sub-pixel groups includes a plurality of first...
US-9,543,284 3D packages and methods for forming the same
Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a...
US-9,543,283 Light emitting diode package and method for manufacturing same
An LED packaging includes a substrate having a top surface and a bottom surface opposite to the top surface, a recess defined in the top surface, an LED mounted...
US-9,543,282 Optical sensor package
One or more embodiments are directed to system in package (SiP) for optical devices, including proximity sensor packaging. One embodiment is directed to an...
US-9,543,281 Semiconductor device having a substrate and input and output electrode units
A plurality of arm elements is arrayed along a first direction of a substrate. Each arm element includes a plurality of semiconductor elements connected in...
US-9,543,280 Light emitting module and lighting device
Disclosed herein are a light emitting module and a lighting device that may be used for a display application or a lighting application. The light emitting...
US-9,543,279 Method of manufacturing a single light-emitting structure
The instant disclosure provides a light-emitting module and a method of manufacturing a single light-emitting structure. The light-emitting module includes two...
US-9,543,278 Semiconductor device with discrete blocks
A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having...
US-9,543,277 Wafer level packages with mechanically decoupled fan-in and fan-out areas
A fan-out microelectronic package is provided in which bond wires electrically couple bond pads on a microelectronic element, e.g., a semiconductor chip which...
US-9,543,276 Chip-stacked semiconductor package
A chip-stacked semiconductor package including a first chip having a plurality of first real bump pads and a plurality of first dummy bump pads, a second chip...
US-9,543,275 Semiconductor package with a lead, package-on-package device including the same, and mobile device including...
A semiconductor package includes a substrate; a first semiconductor chip arranged on the substrate; a second semiconductor chip arranged on the first...
US-9,543,274 Semiconductor device packages with improved thermal management and related methods
Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. The stack...
US-9,543,273 Reduced volume interconnect for three-dimensional chip stack
A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive...
US-9,543,272 Method for interconnecting stacked semiconductor devices
A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The...
US-9,543,271 Semiconductor device having a sealing layer covering a semiconductor memory unit and a memory controller
A semiconductor device includes a substrate, a semiconductor memory unit mounted on a surface of the substrate, a memory controller configured to control the...
US-9,543,270 Multi-device package and manufacturing method thereof
A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip, a plurality of first connectors and a...
US-9,543,269 System-level packaging methods and structures
A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within...
US-9,543,268 Electronic component, method of manufacturing same, composite module including electronic component, and method...
A method of manufacturing a composite module prevents a connection electrode electrically coupled to a functional element from separating from a first principal...
US-9,543,267 Ultra fine pitch wedge for thicker wire
An ultra-fine pitch wedge bonding tool and method for its manufacture are disclosed. The wedge tool is formed with a foot width calculated to enable accurate...
US-9,543,266 Bonding wire for semiconductor device use and method of production of same
Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center...
US-9,543,265 Joint material, and jointed body
Disclosed is a jointed body wherein multiple base members are jointed to each other through a jointing layer, and at least one of the base members is a base...
US-9,543,263 Semiconductor packaging and manufacturing method thereof
The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top...
US-9,543,262 Self aligned bump passivation
A method of fabricating multiple conductor layers utilizing the same seed layer is described. In an embodiment a stud bump structure is described in which the...
US-9,543,261 Designs and methods for conductive bumps
Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor...
US-9,543,260 Segmented bond pads and methods of fabrication thereof
In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first...
US-9,543,259 Semiconductor structure with oval shaped conductor
A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the...
US-9,543,258 Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield
A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground...
US-9,543,257 3DIC interconnect devices and methods of forming same
An interconnect device and a method of forming the interconnect device are provided. Two integrated circuits are bonded together. A first opening is formed...
US-9,543,256 Substrate dividing method
A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method...
US-9,543,255 Reduced-warpage laminate structure
A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively...
US-9,543,254 Chamfered corner crackstop for an integrated circuit chip
A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion...
US-9,543,253 Method for shaping a laminate substrate
A method including providing a laminate substrate, characterizing the laminate substrate for warpage characteristics, determining a horizontal plane distortion...
US-9,543,252 Semiconductor apparatus and method for producing the same
A plurality of semiconductor devices provided on a silicon carbide substrate are provided with electrode layers, respectively. The silicon carbide substrate is...
US-9,543,251 Semiconductor chip and semiconductor package having the same
A semiconductor chip includes a semiconductor substrate having a front surface, a circuit unit formed within the semiconductor substrate and extending from the...
US-9,543,250 Semiconductor devices including through-silicon via
Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being...
US-9,543,249 Package substrate with lateral communication circuitry
A package substrate having a first redistribution layer (RDL1) and a second redistribution layer (RDL2) is disclosed for a multichip package. The first...
US-9,543,248 Integrated circuit devices and methods
An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an...
US-9,543,247 Surface-mount electronic component
A surface-mount chip is formed by a silicon substrate having a front surface and a side. The chip includes a metallization intended to be soldered to an...
US-9,543,246 Semiconductor device
One semiconductor device includes one parallel transistor for connecting in parallel multiple vertical transistors disposed in an active region on a...
US-9,543,245 Semiconductor sensor device and method of producing a semiconductor sensor device
The semiconductor device comprises a substrate (1) of semiconductor material with a front side (4) and an opposite rear side (7), a wiring layer (5) at the...
US-9,543,244 Hybrid package transmission line circuits
"Hybrid" transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are...
US-9,543,243 Low-noise arrangement for very-large-scale integration differential input/output structures
Embodiments of the invention provide low-noise arrangements for very-large-scale integration (VLSI) differential input/output (I/O) structures (I/O pins, solder...
US-9,543,242 Semiconductor package and fabricating method thereof
A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various...
US-9,543,241 Interconnect array pattern with a 3:1 signal-to-ground ratio
An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of...
US-9,543,240 DC-DC converter having terminals of semiconductor chips directly attachable to circuit board
A power supply system has a leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable...
US-9,543,239 Semiconductor device and production method therefor
A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are...
US-9,543,238 Semiconductor device
A semiconductor device includes a center semiconductor chip with a plurality of die pads, a plurality of lead frames, and a plurality of connecting components....
US-9,543,237 Semiconductor package structure
A semiconductor package structure includes a lead frame, a chip and a molding compound. The lead frame includes a tray pad and a plurality of leads. Two of the...
US-9,543,236 Pad configurations for an electronic package assembly
Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening,...
US-9,543,235 Semiconductor package and method therefor
In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the...
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