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Patent # Description
US-9,543,234 In-situ formation of silicon and tantalum containing barrier
A method includes forming an opening in a dielectric layer, and forming a silicon rich layer on a surface of the dielectric layer. A portion of the silicon rich...
US-9,543,233 Chip package having a dual through hole redistribution layer structure
A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a...
US-9,543,232 Semiconductor package structure and method for forming the same
A semiconductor package structure and method for forming the same are provided. The semiconductor package structure includes a substrate and the substrate has a...
US-9,543,231 Stacked semiconductor package
Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper...
US-9,543,230 Semiconductor device and method of manufacturing the same
The semiconductor device includes first interlayer insulating layers and first conductive patterns which are alternately stacked; a second interlayer insulating...
US-9,543,229 Combination of TSV and back side wiring in 3D integration
The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for...
US-9,543,228 Semiconductor device, semiconductor integrated circuit device, and electronic device
A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring...
US-9,543,227 Semiconductor device
A semiconductor device (10) includes a metallic base plate (22) provided with an upper surface (22a) and a lower surface (22b), a plurality of insulating...
US-9,543,226 Heat sink for a semiconductor chip device
A heat sink for a semiconductor chip device includes cavities in a lower surface thereof for receiving electrical components on a top surface of the...
US-9,543,225 Systems and methods for detecting endpoint for through-silicon via reveal applications
Systems and methods for processing a semiconductor wafer includes a plasma processing chamber. The plasma processing chamber includes an exterior, an interior...
US-9,543,224 Hybrid exposure for semiconductor devices
Semiconductor packages and methods, systems, and apparatuses of forming such packages are described. A method of forming a semiconductor package may include...
US-9,543,223 Method and apparatus for fabricating wafer by calculating process correction parameters
A method of calculating an overlay correction model in a unit for the fabrication of a wafer is disclosed. The method comprises measuring overlay deviations of...
US-9,543,222 Methods for measuring the full well capacity of CMOS image sensors
An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An...
US-9,543,221 Method of manufacturing light-emitting apparatus, light-emitting module inspecting apparatus, and method of...
A method of manufacturing a light-emitting apparatus includes disposing a substrate on a support; disposing a light-emitting package including a light-emitting...
US-9,543,220 Substrate processing apparatus, semiconductor device manufacturing method, substrate processing method, and...
According to the present disclosure, it is possible to prevent particles from being generated and to improve substrate processing quality. A substrate...
US-9,543,219 Void monitoring device for measurement of wafer temperature variations
A method of monitoring a temperature of a plurality of regions in a substrate during a deposition process, the monitoring of the temperature including: forming,...
US-9,543,218 Semiconductor component and method for producing a semiconductor component
A method can be used to produce a semiconductor component. A semiconductor layer sequence has an active region that is provided for generating radiation and...
US-9,543,217 Semiconductor device and method of manufacturing semiconductor device
One embodiment includes a vertical n-channel power MOSFET for an output stage and a horizontal p-channel MOSFET for controlling the vertical n-channel power...
US-9,543,216 Integration of hybrid germanium and group III-V contact epilayer in CMOS
A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain...
US-9,543,215 Punch-through-stop after partial fin etch
A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor...
US-9,543,214 Method of forming stressed semiconductor layer
The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed...
US-9,543,213 Asymmetric high-k dielectric for reducing gate induced drain leakage
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes...
US-9,543,212 Preventing over-polishing of poly gate in metal-gate CMP
A method for manufacturing a semiconductor device includes providing a substrate containing a front-end device that includes a first gate in a first-type...
US-9,543,211 Semiconductor structure and manufacturing method thereof
A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain...
US-9,543,210 Forming crown active regions for FinFETs
A method includes forming a first mask over a substrate through a double patterning process, wherein the first mask comprises a horizontal portion and a...
US-9,543,209 Non-planar transistors with replacement fins and methods of forming the same
A method includes forming a first semiconductor fin, and oxidizing surface portions of the first semiconductor fin to form a first oxide layer. The first oxide...
US-9,543,208 Method of singulating semiconductor devices using isolation trenches
In accordance with an embodiment of the present invention, a method for forming a semiconductor device includes forming a device region in a substrate. The...
US-9,543,207 Substrate dividing method
A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method...
US-9,543,206 Wafer die separation
A method of singulating a wafer starts with fracturing the wafer. The method may also include attaching the dicing tape sheet to a ring frame; relatively...
US-9,543,205 Method of fabricating semiconductor device
The method includes disposing semiconductor chips on a package substrate having sawing lines, forming an encapsulant to cover the semiconductor chips on the...
US-9,543,204 Method for manufacturing semiconductor device
In order to provide a semiconductor device that includes a conductive layer on one surface of a semiconductor substrate with an insulating layer therebetween, a...
US-9,543,203 Method of fabricating a semiconductor structure with a self-aligned contact
A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode...
US-9,543,202 Method of fabricating semiconductor device having contact structures
Provided is a method of fabricating a semiconductor device, the method including forming interconnection structures extending parallel to each other on a...
US-9,543,201 Method for forming three-dimensional interconnection, circuit arrangement comprising three-dimensional...
In a method for forming a three-dimensional interconnection, a contact plug is formed within a through hole provided in a substrate and an upper wire formed on...
US-9,543,200 Methods for fabricating semiconductor devices having through electrodes
Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper...
US-9,543,199 Long-term heat treated integrated circuit arrangements and methods for producing the same
An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment....
US-9,543,198 Structure and method for forming interconnect structure
A method for forming a semiconductor structure includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. An...
US-9,543,197 Package with dielectric or anisotropic conductive (ACF) buildup layer
Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to...
US-9,543,196 Methods of fabricating semiconductor devices using nanowires
Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by...
US-9,543,195 Semiconductor process
A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal...
US-9,543,194 Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a first insulator, and conductors and second insulators alternately provided on the first insulator. Each...
US-9,543,193 Non-hierarchical metal layers for integrated circuits
An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first...
US-9,543,192 Stitched devices
A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled...
US-9,543,191 Wiring structure having interlayer insulating film and wiring line without a barrier layer between
Provided are a semiconductor device and semiconductor-device manufacturing method that make it possible to improve the contact between an insulating film and a...
US-9,543,190 Method of fabricating semiconductor device having a trench structure penetrating a buried layer
A method of fabricating a semiconductor device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a buried layer in...
US-9,543,189 Laminated wafer processing method
A method of processing a laminated wafer in which a first wafer is laminated on a second wafer, the method including: a laminated wafer forming step of forming...
US-9,543,188 Isolation structure, method for manufacturing the same, and semiconductor device having the structure
The present invention provides an isolation structure for a semiconductor substrate and a method for manufacturing the same, as well as a semiconductor device...
US-9,543,187 Electrostatic chuck
In accordance with an embodiment of the invention, there is provided an electrostatic chuck comprising an electrode, and a surface layer activated by a voltage...
US-9,543,186 Substrate support with controlled sealing gap
Embodiments of substrate supports are provided herein. In some embodiments, a substrate support may include a support plate having a support surface to support...
US-9,543,185 Packaging process tools and systems, and packaging methods for semiconductor devices
Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for...
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