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Patent # Description
US-9,543,184 Electrostatic chuck
The present invention is an electrostatic chuck including a ceramic base body and an adsorption electrode provided inside of or on the lower surface of the...
US-9,543,183 Heated electrostatic chuck and semiconductor wafer heater and methods for manufacturing same
A heated electrostatic chuck is provided, including a base having an upper surface and peripheral side surfaces, a thermal barrier coating formed by plasma...
US-9,543,182 Electrostatic chuck and method of manufacturing semiconductor device
An electrostatic chuck device including: a plurality of adsorption areas having an electrode generating electrostatic attractive force; and a control portion...
US-9,543,181 Replaceable electrostatic chuck sidewall shield
A replaceable electrostatic chuck sidewall shield is provided. The replaceable electrostatic chuck sidewall shield fills or partially fills an indentation...
US-9,543,180 Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum
An integrated transport device for a wafer carrier includes: an evacuatable chamber for accommodating therein a wafer carrier having a front opening with a...
US-9,543,179 Load port module
A load port module includes a plate to support at least one substrate, a sensor to detect foreign matter at a predetermined location, and a cleaner to remove...
US-9,543,178 Semiconductor wafer stocker apparatus and wafer transferring methods using the same
A semiconductor wafer stocker apparatus includes a body frame, an inlet port to load a wafer shipping box into the body frame, an outlet port to unload the...
US-9,543,177 Pod and purge system using the same
An object is to prevent the partial pressure of oxidative gas over time in an FOUP mounted on an FIMS system and left open. A surface purge unit is provided on...
US-9,543,176 Operating methods of purge devices for containers
Operating methods of purge devices for containers are provided. The operating methods comprise a step of aligning an opening of a container to a first purging...
US-9,543,175 Package assembly for thin wafer shipping and method of use
A package assembly for thin wafer shipping using a wafer container and a method of use are disclosed. The package assembly includes a shipping container and a...
US-9,543,174 Cassette configurations to support platters having different diameters
A material handling apparatus adapted to support a plurality of disc-shaped platters, such as but not limited to a cassette assembly adapted to support data...
US-9,543,173 Decapsulator with applied voltage and etchant cooling system for etching plastic-encapsulated devices
An apparatus and a method for selectively etching an encapsulant forming a package of resinous material around an electronic device includes an electronic...
US-9,543,172 Apparatus for providing and directing heat energy in a process chamber
Apparatus for providing heat energy to a process chamber are provided herein. The apparatus may include a process chamber body of the process chamber, a solid...
US-9,543,171 Auto-correction of malfunctioning thermal control element in a temperature control plate of a semiconductor...
A method for auto-correction of at least one malfunctioning thermal control element among an array of thermal control elements that are independently...
US-9,543,170 Semiconductor packages and methods of forming the same
Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die...
US-9,543,169 Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing...
A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the...
US-9,543,168 Defects annealing and impurities activation in semiconductors at thermodynamically non-stable conditions
A symmetric multicycle rapid thermal annealing (SMRTA) method for annealing a semiconductor material without the material decomposing. The SMRTA method includes...
US-9,543,167 FinFET source-drain merged by silicide-based material
A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a first diamond shaped epitaxial layer...
US-9,543,166 External gettering method and device
Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be...
US-9,543,165 Method of fabricating semiconductor device
A method for fabricating a semiconductor device includes forming a first hard mask (HM) layer over a material layer, forming a patterned second HM layer over...
US-9,543,164 Etching method
An etching method is provided for performing an etching process on an etching target film arranged on a substrate. The etching method includes the steps of...
US-9,543,163 Methods for forming features in a material layer utilizing a combination of a main etching and a cyclical...
Methods for etching a material layer disposed on the substrate using a combination of a main etching step and a cyclical etching process are provided. The...
US-9,543,162 Substrate processing method
A substrate processing method includes a phosphoric acid processing step of supplying a phosphoric acid aqueous solution, which contains silicon and has a...
US-9,543,161 Method of planarizating film
A method of fabricating a semiconductor device is disclosed. The method includes forming a flowable-material (FM) layer over a substrate. The substrate has a...
US-9,543,160 Reducing defects in patterning processes
A method includes forming a mask layer forming a first photo resist over the mask layer, performing a first patterning step on the first photo resist, and...
US-9,543,159 Patterning process of a semiconductor structure with a wet strippable middle layer
A lithography method is provided in accordance with some embodiments. The lithography method includes forming an under layer of a polymeric material on a...
US-9,543,158 Technique to deposit sidewall passivation for high aspect ratio cylinder etch
Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a substrate. Separate etching and...
US-9,543,157 Method for processing a carrier, a method for operating a plasma processing chamber, and a method for...
According to various embodiments, a method for processing a carrier may include: performing a dry etch process in a processing chamber to remove a first...
US-9,543,156 Method for growing graphene on surface of gate electrode and method for growing graphene on surface of...
The present invention provides a method for growing graphene on a surface of a gate electrode and a method for growing graphene on a surface of a source/drain...
US-9,543,155 Method of forming minute patterns and method of manufacturing a semiconductor device using the same
A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the...
US-9,543,154 Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device includes the following steps. A semiconductor substrate is prepared which has a first main surface and a...
US-9,543,153 Recess technique to embed flash memory in SOI technology
An integrated circuit arranged on a silicon-on-insulator (SOI) substrate region is provided. The SOI substrate region is made up of a handle wafer region, an...
US-9,543,152 MIM capacitors for leakage current improvement
The semiconductor device includes a substrate, a bottom electrode, a capacitor dielectric layer, a top electrode, an etching stop layer, a first anti-reflective...
US-9,543,151 Ionizer and substrate transfer system having the same, and method of manufacturing a semiconductor device using...
An ionizer includes a body extending in a first direction, a sheath gas nozzle installed in a lower portion of the body and having a spray hole and an electrode...
US-9,543,150 Systems and methods for forming ultra-shallow junctions
A method for forming a junction on a substrate includes removing a native oxide layer of a bulk material; doping an outer layer of the bulk material with...
US-9,543,149 High voltage lateral extended drain MOS transistor with improved drift layer contact
An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain end diffused link between the buried drift region...
US-9,543,148 Mask shrink layer for high aspect ratio dielectric etch
Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor...
US-9,543,147 Photoresist and method of manufacture
A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating additive in order to form a floating...
US-9,543,146 Manufacturing method of semiconductor device that includes forming plural nitride semiconductor layers of...
According to one embodiment, a manufacturing method of a semiconductor device, comprising: forming a first nitride semiconductor layer on a substrate using a...
US-9,543,145 Manufacturing method of semiconductor device
A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a...
US-9,543,144 Vapor deposition of chalcogenide-containing films
Chalcogenide-containing film forming compositions, methods of synthesizing the same, and methods of forming Chalcogenide-containing films on one or more...
US-9,543,143 Method for producing amorphous oxide thin film and thin film transistor
A method for producing an amorphous oxide thin film includes: a pre-treatment process of selectively changing a binding state of an organic component, at a...
US-9,543,142 Semiconductor nanocrystals and methods
In one embodiment, a method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals...
US-9,543,141 Method for curing flowable layer
Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a flowable layer over a substrate...
US-9,543,140 Deposition of boron and carbon containing materials
Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as...
US-9,543,139 In-situ support structure for line collapse robustness in memory arrays
Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures...
US-9,543,138 Ion optical system for MALDI-TOF mass spectrometer
An ion accelerator for a time-of-flight mass spectrometer includes a pulsed ion accelerator positioned proximate to a sample plate and having an electrode that...
US-9,543,137 Sample droplet generation from segmented fluid flow and related devices and methods
A sample droplet generator transforms a segmented array of sample material into a continuous stream of droplets containing analytes. The droplets may serve as a...
US-9,543,136 Ion optics components and method of making the same
A method of making an ion optics component includes providing an electrically isolating substrate and machining away material of the substrate from at least one...
US-9,543,135 Mass spectrometer and mass analyzing method for efficiently ionizing a sample with less carry-over
A mass spectrometer for efficiently ionizing a sample with less carry-over. The ratio of the amount of sample gas to that of a whole headspace gas is increased...
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