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Non-volatile memory and a method of operating the same
A non-volatile memory includes a current sensing checking block including a programming status input block comprising a plurality of sub-blocks connected with...
Semiconductor memory device, control method, and memory system
According to one embodiment, a semiconductor memory device includes a memory cell array, a first circuit, and a second circuit. The first circuit executes...
Nonvolatile memory device, memory system including the same, and method of
operating nonvolatile memory device
A non-volatile memory device includes a non-volatile memory cell array including a plurality of word lines, a voltage generator configured to generate a first...
Semiconductor device to improve reliability of read operation for memory
A semiconductor device includes memory cells; an operation circuit suitable for performing a read operation on the memory cells; and a check circuit suitable...
Sense amplifier design for ramp sensing
Methods and systems for sensing memory cells using a sense amplifier that can support both ramp sensing and conventional sensing are described. With ramp...
Non-volatile semiconductor memory device and reading method for
non-volatile semiconductor memory device that...
A non-volatile semiconductor memory device includes a memory cell, and a sense amplifier that includes a latch unit, a first transistor having a first end...
Word line dependent temperature compensation scheme during sensing to
counteract cross-temperature effect
Methods for reducing cross-temperature dependent word line failures using a temperature dependent sensing scheme during a sensing operation are described. In...
Memory chip, memory device, and reading method
A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect...
Nonvolatile memory device and operating method thereof
An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit...
Storage control system with power-off time estimation mechanism and method
of operation thereof
A storage control system, and a method of operation thereof, including: a power-down module for powering off a memory sub-system; a decay estimation module,...
Nonvolatile memory erasure techniques
Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before...
Partial block erase for block programming in non-volatile memory
A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A...
Semiconductor memory device
A semiconductor memory device includes first and second plugs formed on a semiconductor substrate, a word line between the first and second plugs and above the...
Semiconductor device and programming method thereof
A semiconductor device includes a plurality of electrically coupled memory cells in a generally vertical configuration extending in a generally perpendicular...
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes an array of memory cells arranged at the position intersecting positions of the word line and the bit line, a...
Error corrected pre-read for upper page write in a multi-level cell memory
Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of...
Non-volatile memory with a variable polarity line decoder
The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the...
End-of-life reliability for non-volatile memory cells
A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines...
Low power high speed program method for multi-time programmable memory
A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps...
Memory array and coupled TCAM architecture for improved access time during
A memory device includes a first ternary content addressable memory (TCAM), a second TCAM, a memory array coupled to the first and second TCAMs, a first...
Memory circuits using a blocking state
A memory circuit with blocking states. In one embodiment, the memory circuit includes a two non-volatile transistors connected in series. The input state of the...
Magnetic tunnel junction ternary content addressable memory
A Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) employing six transistors and exhibiting reduced standby leakage and improved...
System for writing data in a memory
A system including: a first memory including several portions of one or more pages each, said memory including first and second ports that can simultaneously...
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of...
Resistive memory and measurement system thereof
A measurement system including a testing machine and a resistive memory is provided. The resistive memory includes a first storage cell. The first storage cell...
Multiple layer forming scheme for vertical cross point reram
Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point...
Electronic device having semiconductor storage cells
Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic...
Semiconductor device including memory cell and sense amplifer, and IC card
including semiconductor device
A semiconductor device includes a memory cell; circuitry that generates a reference voltage; and a sense amplifier including a first input terminal electrically...
Non-volatile memory cell and non-volatile memory device
A non-volatile memory cell and a non-volatile memory device are provided. The non-volatile memory cell includes a latch structure, a first read/write circuit, a...
Multistage memory cell read
A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce...
Provision of holding current in non-volatile random access memory
Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In...
Memory array plane select
Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged...
Nonvolatile semiconductor memory device
The transistor layer is disposed above or below the memory layer and includes a transistor. The wiring line layer connects the memory layer and the transistor...
Programming memory cells
First threshold voltages of one or more memory cells in a memory array are obtained. For each memory cell in the one or more memory cells, a target threshold...
Determining soft data for combinations of memory cells
The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of...
A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is...
Write assist circuit integrated with leakage reduction circuit of a static
random access memory for increasing...
A transient voltage collapse circuit provides a reference voltage for an SRAM (static random access memory). The SRAM receives a first reference voltage and a...
Memory architecture with local and global control circuitry
A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The...
Device with SRAM memory cells including means for polarizing wells of
memory cell transistors
A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and...
Threshold voltage mismatch compensation sense-amplifiers for static random
access memories with multiple...
Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline...
Retention control in a memory device
A memory device and method of operating the memory device are provided. The memory device has bitcells arranged in a plurality of rows and columns. Row driver...
Leakage-current abatement circuitry for memory arrays
In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit...
SRAM core cell design with write assist
A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access...
Single-ended signal equalization with a programmable 1-tap decision
An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) receive a sequence of input values that have been carried...
Semiconductor memory device and method for accessing the same
A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device includes an oxide heterojunction transistor...
Circuit and method for controlling MRAM cell bias voltages
A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without...
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a memory cell, a bit line connected to the memory cell, a sense circuit which senses data of...
Magnetic memory cells with low switching current density
Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a substrate defined with a memory cell region. A cell selector unit...
Low power input gating
Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated...
The present disclosure includes methods and systems for channel skewing. One or more methods for channel skewing includes providing a number of groups of data...