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Patent # Description
US-9,542,229 Multiple core real-time task execution
A real-time task may initially be performed by a first thread that is executing on a first core of a multi-core processor. A second thread may be initiated to...
US-9,542,228 Image processing apparatus, control method thereof and storage medium
To accomplish this, an image processing apparatus, in response to a start-up request for an application, reads a class file of a class of the application, adds,...
US-9,542,227 Parallel dynamic memory allocation using a lock-free FIFO
One embodiment of the present invention sets forth a technique for dynamically allocating memory using one or more lock-free FIFOs. One or more lock-free FIFOs...
US-9,542,226 Operating programs on a computer cluster
A mechanism is provided for operating programs on a computer cluster comprising cluster resources. The cluster resources comprise non-virtual real hardware...
US-9,542,225 Method and apparatus for determining allocation design of virtual machines
A disclosed method includes: receiving a request to allocate one or plural virtual machines for a system that includes the one or plural virtual machines to one...
US-9,542,224 User space function execution from a kernel context for input/output filtering from a thread executing in the...
The approaches described herein implement execution of a user space operation from a kernel context. A thread, executing on a computing device, initializes a...
US-9,542,223 Scheduling jobs in a cluster by constructing multiple subclusters based on entry and exit rules
Jobs are scheduled in a cluster comprising multiple computing nodes. The scheduling of jobs includes defining rules for constructing virtual sub-clusters of the...
US-9,542,222 Resource broker system for dynamically deploying and managing software services in a virtual environment based...
A system and method can deploy and manage software services in virtualized and non-virtualized environments. The system provides an enterprise application...
US-9,542,221 Dynamic co-scheduling of hardware contexts for parallel runtime systems on shared machines
Multi-core computers may implement a resource management layer between the operating system and resource-management-enabled parallel runtime systems. The...
US-9,542,220 System and method for supporting resource manager (RM) instance awareness in a transactional environment
A system and method can support transaction processing in a transactional environment. A transactional server operates to receive resource manager (RM) instance...
US-9,542,219 Automatic analysis based scheduling of jobs to appropriate cloud resources
Systems, methods, and computer program products to perform an operation comprising identifying a set of attributes of an application specified in a request to...
US-9,542,218 Migrating virtual machines based on relative priority of virtual machine in the context of a target hypervisor...
A method, system and computer program product for selecting a target hypervisor to run a migrated virtual machine. An "effective priority value," representing...
US-9,542,217 System, method, and recording medium
A system that compares first information corresponding to an amount of a first type of resource used when a first virtual machine is executed in an idle state...
US-9,542,216 Richer model of cloud app markets
In a cloud app market, a cloud infrastructure customer can purchase apps for performing services such as rootkit detection and network security for a customer...
US-9,542,215 Migrating virtual machines from a source physical support environment to a target physical support environment...
Migration of a pool of virtual machines to a target physical machine. The virtual machines were all provisioned into an initial state using a master image....
US-9,542,214 Operating system virtualization for host channel adapters
A host information handling system (IHS) provides virtualization of host channel adapters (HCAs). A hypervisor partitions a system memory of the host IHS into...
US-9,542,213 Method and system for identifying virtualized operating system threats in a cloud computing environment
Systems for monitoring a virtual machine in a cloud computing environment are disclosed. The systems include a baseline module residing on the virtual machine...
US-9,542,212 Loading a machine code API onto an 8-bit virtual machine to enable new functionality
A compact, register-based, eight-bit virtual machine is realized on a resource-constrained device such as, for example, an IR remote control device. The IR...
US-9,542,211 Co-designed dynamic language accelerator for a processor
In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output...
US-9,542,210 Ensuring determinism during programmatic replay in a virtual machine
Aspects of an application program's execution which might be subject to non-determinism are performed in a deterministic manner while the application program's...
US-9,542,209 Preserving user profiles across remote desktop sessions
User profiles of remote desktops are managed in a crash-consistent manner. When a user logs into a remote desktop, metadata of the user profile is loaded from...
US-9,542,208 System and method to integrate/setup multiple branded applications in the setup wizard
Systems and methods for setting up carrier applications within a setup wizard are disclosed. In some implementations, a computing device launches an operating...
US-9,542,207 Plurality of interface files usable for access to BIOS
A computer may comprise a processor and first storage device coupled to the processor. The first storage device contains a basic input/output system (BIOS)...
US-9,542,206 Controlling the configuration of computer systems
Embodiments relate to controlling configuration of a computer system comprising one or more exchangeable components. The exchangeable components comprising...
US-9,542,205 Configuring a data center
Embodiments of the present disclosure disclose a method and an apparatus for configuring a data center. The method comprises obtaining a function call...
US-9,542,204 Architectural mode configuration
A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of...
US-9,542,203 Universal dock for context sensitive computing device
A dock for interacting with a computing device. The computing device configures itself for operations based on its context, which may be determined form the...
US-9,542,202 Displaying and updating workspaces in a user interface
Providing a bridge interface for managing virtual workspaces is disclosed. A plurality of workspace images is presented in a user interface, each workspace...
US-9,542,201 Network bios management
A computer system can obtain BIOS data from a network storage by a management controller of the computer system. The computer system can emulate a BIOS memory...
US-9,542,200 Dynamic port naming in a chassis
A tool for dynamically naming network ports and switch ports in a chassis. The tool retrieves, by one or more computer processors, chassis specifications of the...
US-9,542,199 Method of managing a solid state drive, associated systems and implementations
One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during...
US-9,542,198 System and methods for dynamic management of hardware resources
A dynamically reconfigurable framework manages processing applications in order to meet time-varying constraints to select an optimal hardware architecture. The...
US-9,542,197 Router and a virtual trusted runtime BIOS
An implementation may include a virtual trusted runtime BIOS managed by the virtual machine monitor. A replacement portion of the virtual trusted runtime BIOS...
US-9,542,196 Communication terminal and method for providing configuration data for a modem with system boot firmware
A communication terminal is described comprising a modem; a first memory configured to store configuration data for the modem; a second memory configured to...
US-9,542,195 Motherboards and methods for BIOS failover using a first BIOS chip and a second BIOS chip
Systems and methods for BIOS failover. A processor reset is detected and a timer is set to expire after a predetermined time corresponding to a time to complete...
US-9,542,194 Speculative register file read suppression
A single threaded out-of-order processor 2 includes an architected register file 22 and a speculative register file 20. Speculative register allocation...
US-9,542,193 Memory address collision detection of ordered parallel threads with bloom filters
A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store...
US-9,542,192 Tokenized streams for concurrent execution between asymmetric multiprocessors
A method for executing an application program using streams. A device driver receives a first command within an application program and parses the first command...
US-9,542,191 Hardware profiling mechanism to enable page level automatic binary translation
A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime...
US-9,542,190 Processor with fetch control for stoppage
A data processor of an embodiment includes a memory, an instruction cache, a processing unit (CPU), and a fetch process control unit. The memory stores a...
US-9,542,189 Heuristics for improving performance in a tile-based architecture
One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in...
US-9,542,188 Hardware debugging apparatus and method for software pipelined program
Provided is a hardware debugging apparatus and method for a software-pipelined program. The hardware debugging apparatus and method overcome a currency problem...
US-9,542,187 Guest instruction block with near branching and far branching sequence construction to native instruction block
A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch...
US-9,542,186 Instruction set for supporting wide scalar pattern matches
A processor includes an instruction decoder to receive an instruction having a first operand, a second operand, and a third operand, and an execution unit...
US-9,542,185 Allocation method, apparatus, and program for managing architectural registers and physical registers using...
An allocation system and a method for allocating an architectural register in a system having one or more mapping tables. When the allocation system detects a...
US-9,542,184 Local instruction loop buffer utilizing execution unit register file
A circuit arrangement utilizes a register file of an execution unit as a local instruction loop buffer to enable suitable algorithms, such as DSP algorithms, to...
US-9,542,183 Branch synthetic generation across multiple microarchitecture generations
Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node...
US-9,542,182 Standardization of variable names in an integrated development environment
A method for providing for standardization of variable names in an integrated development environment is provided. The method includes scanning a project source...
US-9,542,181 Software component configuration identification
An identification method is provided. The method includes generating dictionaries comprising a product taxonomy and associated base entities comprising sub-sets...
US-9,542,180 Vehicle configuration driven loading of software parts
A system and method of loading software parts on a vehicle. Information identifying a desired software configuration for active software parts on the vehicle is...
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