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Patent # Description
US-9,548,385 Self-aligned contacts for vertical field effect transistors
Semiconductor devices having vertical field effect transistors with self-aligned source and drain contacts are provided, as well as methods for fabricating...
US-9,548,384 Conductive spline for metal gates
An integrated circuit may include a metal gate which extends over an active area and onto an isolation dielectric layer. A conductive spline is formed on the...
US-9,548,383 HEMT with a metal film between the gate electrode and the drain electrode
A compound semiconductor device includes a channel layer of first arsenide semiconductor, an electron supply layer of second arsenide semiconductor over the...
US-9,548,382 Spintronic device
Provided in one embodiment is a device, comprising: a substrate; and a layer disposed over the substrate, wherein the layer comprises a monolayer of crystals...
US-9,548,381 Method and structure for III-V nanowire tunnel FETs
A heterojunction tunnel field effect transistor (TFET) has a channel region that includes a first portion of a nanowire, a source region and a drain region that...
US-9,548,380 Non-volatile memory cell having a trapping charge layer in a trench and an array and a method of manufacturing...
A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region...
US-9,548,379 Asymmetric multi-gate FinFET
An asymmetrical finFET device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The fin extends along a length of the...
US-9,548,378 Epitaxial channel formation methods and structures
A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one...
US-9,548,377 Thermal treatment for reducing transistor performance variation in ferroelectric memories
Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those...
US-9,548,376 Method of manufacturing a semiconductor device including a barrier structure
A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer over...
US-9,548,375 Vertical diode and fabrication method thereof
A vertical diode is provided. The vertical diode includes a high-voltage N-type well region in a substrate, and two P-doped regions spaced apart from each other...
US-9,548,374 High power insulated gate bipolar transistors
A method of forming a transistor device include forming a drift layer of a first conductivity type, forming a well of a second conductivity type in the drift...
US-9,548,373 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a control gate electrode; and an organic molecular layer,...
US-9,548,372 Semiconductor device with tunable work function
The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, a barrier layer...
US-9,548,371 Integrated circuits having nickel silicide contacts and methods for fabricating the same
Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary...
US-9,548,370 Transistor device with integrated gate-resistor
A transistor device includes an individual transistor cell arranged in a transistor cell field on a semiconductor body, the individual transistor cell having a...
US-9,548,369 Memory device and method of manufacturing the same
Provided is a memory device including a substrate, a first stack structure, and a plurality of second stack structures. The substrate has a first region and a...
US-9,548,368 Semiconductor device including ion gel material and electronic device including the semiconductor device
A semiconductor device, a method for manufacturing the same, and an electronic device including the same are provided. The semiconductor device includes a first...
US-9,548,367 Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching and the FinFETs thereof
An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin...
US-9,548,366 Self aligned contact scheme
An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard...
US-9,548,365 Semiconductor device and method for manufacturing semiconductor device
A semiconductor device includes: a buffer layer formed over a substrate; a first semiconductor layer formed over the buffer layer by using a compound...
US-9,548,364 Structures and methods relating to graphene
This application relates to graphene based heterostructures and methods of making graphene based heterostructures. The graphene heterostructures comprise: i) a...
US-9,548,363 Extreme high mobility CMOS logic
A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS...
US-9,548,362 High mobility devices with anti-punch through layers and methods of forming same
An embodiment semiconductor device includes a fin extending upwards from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having...
US-9,548,361 Method of using a sacrificial gate structure to make a metal gate FinFET transistor
A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the...
US-9,548,360 Semiconductor component and manufacturing method thereof
A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that...
US-9,548,359 Methods for forming vertical semiconductor pillars
A method for forming a semiconductor device includes providing a semiconductor structure, which includes a semiconductor substrate and a first mask layer on the...
US-9,548,358 Dual fill silicon-on-nothing field effect transistor
A patterned stack of a first silicon-germanium alloy nanowire, a second silicon-germanium alloy nanowire, and a silicon-containing nanowire is formed on a...
US-9,548,357 Shallow trench isolation structure with sigma cavity
Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication. The shallow trench isolation cavity...
US-9,548,356 Shallow trench isolation structures
Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms...
US-9,548,355 Compound finFET device including oxidized III-V fin isolator
A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further...
US-9,548,354 Semiconductor devices and methods for fabricating the same
A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first...
US-9,548,353 Wide band-gap semiconductor device including schotky electrode and method for producing same
A semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode being in contact...
US-9,548,352 Semiconductor device with field threshold MOSFET for high voltage termination
This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and...
US-9,548,351 Radio frequency isolation for SOI transistors
According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the...
US-9,548,350 High quality factor capacitors and methods for fabricating high quality factor capacitors
Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a...
US-9,548,349 Semiconductor device with metal extrusion formation
Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication...
US-9,548,348 Methods of fabricating an F-RAM
Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are...
US-9,548,347 Semiconductor device and method of forming an inductor on polymer matrix composite substrate
A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over...
US-9,548,346 Display unit, method of manufacturing the same, and electronic apparatus
A display unit includes: a display layer including a pixel electrode; a semiconductor layer provided in a layer below the display layer, the semiconductor layer...
US-9,548,345 Display screen having organic light-emitting diodes
The invention relates to a matrix display screen which includes, in sequence: a mounting (50); at least one first metal portion (156); a stack of layers (52,...
US-9,548,344 Organic light-emitting display apparatus and method of manufacturing the same
An organic light-emitting display apparatus including a substrate; a thin-film transistor (TFT) arranged on the substrate; a black matrix located between the...
US-9,548,343 Flexible display
A flexible display includes: a first flexible substrate; an intermediate barrier layer positioned on the first flexible substrate and comprising silicon oxide;...
US-9,548,342 Organic white light emitting display apparatus
Disclosed is an organic white light emitting display apparatus. The organic white light emitting device includes a first substrate including a first sub-pixel...
US-9,548,341 Organic light emitting diode display
OLED display that includes: a substrate; a plurality of thin film transistors formed on the substrate; a plurality of first electrodes respectively connected to...
US-9,548,340 Ambient and infrared (IR) light sensing in organic light emitting diode (OLED) display
A method and apparatus for an OLED display system is presented. A substrate is provided and a display is provided on the substrate. At least one sensor is also...
US-9,548,339 Organic light emitting diode display device
An organic light emitting diode (OLED) display device includes: a first substrate comprising red, green, and blue pixel areas; a first electrode on the first...
US-9,548,338 Display substrate and display device applying the same
A display substrate and a display device applying the same are provided. The display substrate includes a base plate and a display structure. The display...
US-9,548,337 Image sensor and electronic device including the same
An image sensor including a semiconductor substrate integrated with a plurality of photo-sensing devices and a nanopattern layer on the semiconductor substrate,...
US-9,548,336 Image sensors and electronic devices including the same
Image sensors, and electronic devices including the same, include a first photo-sensing device sensing light in a full visible to near infrared ray region, a...
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