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Patent # Description
US-9,548,335 Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data...
US-9,548,334 Magnetic tunnel junction with perpendicular enhancement layer and thin reference layer
The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory...
US-9,548,333 MRAM integration with low-K inter-metal dielectric for reduced parasitic capacitance
Systems and methods of integration of resistive memory elements with logic elements in advanced nodes with improved mechanical stability and reduced parasitic...
US-9,548,332 Method of forming a micro LED device with self-aligned metallization stack
A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, a patterned...
US-9,548,331 Manufacturing method of quantum dot light emitting diode
A quantum dot light emitting diode, including a first electrode and a second electrode, a quantum dot light emitting layer disposed between the two electrodes,...
US-9,548,330 Method for producing semiconductor light receiving device and semiconductor light receiving device
A method for producing a semiconductor light receiving device includes the steps of growing a stacked semiconductor layer on a principal surface of a substrate,...
US-9,548,329 Backside illuminated image sensor and method of manufacturing the same
A backside illuminated (BSI) image sensor device includes: a first substrate including a front side and a back side; a second substrate bonded with the first...
US-9,548,328 Solid-state image sensor and camera
A solid-state image sensor is provided. The sensor includes a substrate having a light-receiving surface. The substrate includes a charge accumulation portion...
US-9,548,327 Imaging device having a selenium containing photoelectric conversion layer
To provide an imaging device capable of obtaining high-quality imaging data. The imaging device includes a first circuit and a second circuit. The first circuit...
US-9,548,326 Solid-state imaging device, method of manufacturing a solid-state imaging device, and electronic apparatus
Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix...
US-9,548,325 Method for manufacturing a thin film transistor array panel
A thin film transistor array panel includes a substrate, an insulation layer, a first semiconductor, and a second semiconductor. The insulation layer is...
US-9,548,324 Array substrate and method for fabricating the same
An array substrate and a method for fabricating the same are disclosed. The method includes steps of providing a substrate (20), a first metal layer including...
US-9,548,323 Thin film transistor display panel and method of manufacturing the same
A thin film transistor array panel includes: a first gate line extending in a first direction; a second gate line extending in the first direction; a data line...
US-9,548,322 Display device
According to one embodiment, a wiring substrate includes a pad group of a first pad to supply a power source voltage of low level, a second pad to supply a...
US-9,548,321 Method of manufacturing thin film transistor (TFT) array substrate
A thin film transistor (TFT) array substrate is provided that includes a TFT on a substrate. The TFT can include an active layer, gate electrode, source...
US-9,548,320 Heterogeneous semiconductor material integration techniques
Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a...
US-9,548,319 Structure for integration of an III-V compound semiconductor on SOI
A semiconductor-on-insulator (SOI) substrate is provided that includes a silicon or germanium handle substrate that is miscut from 2 degrees to 8 degrees...
US-9,548,318 Connecting to back-plate contacts or diode junctions through a RMG electrode and resulting devices
Methods to connect to back-plate (BP) or well contacts or diode junctions through a RMG electrode in FDSOI technology based devices and the resulting devices...
US-9,548,317 FDSOI semiconductor structure and method for manufacturing the same
The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises...
US-9,548,316 Semiconductor device
A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a...
US-9,548,315 Nonvolatile semiconductor memory device, method of manufacturing the same, and method of measuring the same
A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped...
US-9,548,314 Method of making a non-volatile memory (NVM) with trap-up reduction
A method for forming a semiconductor device includes forming a select gate over a substrate and forming a charge storage layer and a control gate over the...
US-9,548,313 Method of making a monolithic three dimensional NAND string using a select gate etch stop layer
A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate,...
US-9,548,312 Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure...
A method includes providing a semiconductor structure including a nonvolatile memory cell element and one or more electrically insulating layers covering the...
US-9,548,311 Non-volatile storage element with suspended charge storage region
Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices....
US-9,548,310 Semiconductor device
According to an embodiment, a semiconductor device includes a semiconductor substrate, a first region that is provided on the semiconductor substrate and has a...
US-9,548,309 Semiconductor devices including a dummy gate structure on a fin
Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The...
US-9,548,308 Semiconductor device
A nonvolatile memory is provided. A semiconductor device (a nonvolatile memory) has a circuit configuration similar to that of a general SRAM. By providing a...
US-9,548,307 Compact CMOS device isolation
An integrated circuit includes a first well of the first conductivity type formed in a semiconductor layer where the first well housing active devices and being...
US-9,548,306 Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect...
In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate...
US-9,548,305 Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture are disclosed. A representative transistor device includes two fins over a workpiece. An insulating material is...
US-9,548,304 Semiconductor device including gate structure for threshold voltage modulation in transistors and method for...
A method for fabricating a semiconductor device includes forming an NMOS region and a PMOS region in a substrate, forming a first stack layer including a first...
US-9,548,303 FinFET devices with unique fin shape and the fabrication thereof
A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a...
US-9,548,302 Semiconductor integrated circuit
A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate....
US-9,548,301 Semiconductor devices including a stressor in a recess and methods of forming the same
Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench...
US-9,548,300 Semiconductor device including capacitor and method for manufacturing the same
A semiconductor device includes a semiconductor substrate having a first region and a second region; a first planar type capacitor including a gate electrode...
US-9,548,299 Semiconductor device
A semiconductor device provides reduced size and increased performance, and includes a semiconductor layer having a surface layer including first and second...
US-9,548,298 Method of improving bipolar device signal to noise performance by reducing the effect of oxide interface...
An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base...
US-9,548,297 Semiconductor device and method for manufacturing same
Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a PIP capacitor located. The PIP...
US-9,548,296 Semiconductor electrostatic protection circuit device
An electrostatic protection circuit in a semiconductor device includes a first first-conductivity type well extending in a first direction over a semiconductor...
US-9,548,295 System and method for an integrated circuit having transistor segments
In accordance with an embodiment, an integrated circuit has a first transistor made of a plurality of first transistor segments disposed in a well area, and a...
US-9,548,294 Semiconductor device with temperature-detecting diode
A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed...
US-9,548,293 III-nitride based ESD protection device
An ESD (electrostatic discharge) protection device includes a first III-nitride p-i-n diode and a second III-nitride p-i-n diode connected to the first...
US-9,548,292 Circuit including a resistive element, a diode, and a switch and a method of using the same
An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction...
US-9,548,291 Photomask and semiconductor structure
Provided is a semiconductor structure. The semiconductor structure is formed on a substrate, and includes a first region and a second region surrounded by the...
US-9,548,290 Semiconductor device having magnetic alignment marks and underfill resin layers
A semiconductor device includes a semiconductor element, a connection electrode formed on the semiconductor element, and alignment marks formed on the...
US-9,548,289 Semiconductor package assemblies with system-on-chip (SOC) packages
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor...
US-9,548,288 Integrated circuit die decoupling system with reduced inductance
A system that includes an integrated circuit die and a power supply decoupling unit is disclosed. The system includes an integrated circuit die, and...
US-9,548,287 LED module having LED chips as light source
An LED (Light Emitting Diode) module includes an LED unit having one or more LED chips and a case. The case includes: a body including a base plate made of...
US-9,548,286 Solid state lights with thermal control elements
A solid state light ("SSL"), a solid state emitter ("SSE"), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging...
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