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Patent # Description
US-9,548,285 Method of manufacturing semiconductor device
Reliability of a semiconductor device is improved. A method of manufacturing the semiconductor device includes a step of cutting a tab suspension lead from a...
US-9,548,284 Reduced expansion thermal compression bonding process bond head
Embodiments of a thermal compression bonding process bond head and a method for producing a thermal compression bonding process bond head are disclosed. In some...
US-9,548,283 Package redistribution layer structure and method of forming same
A package-on-package (PoP) device comprises a bottom package on a substrate and a first set of conductive elements coupling the bottom package and the...
US-9,548,282 Metal contact for semiconductor device
A semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate (300) provided with a plurality of pads...
US-9,548,281 Electrical connection for chip scale packaging
A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the...
US-9,548,280 Solder pad for semiconductor device package
A solder ball pad for mounting a solder ball of a semiconductor device for preventing delamination of an overlying dielectric layer, and particularly devices...
US-9,548,279 Connection member, semiconductor device, and stacked structure
A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal...
US-9,548,278 Methods and apparatus for passive equalization in high-speed and high density integrated circuits
A passive equalization structure is provided. The passive equalization structure includes a semiconductor substrate having first and a differential pair having...
US-9,548,277 Integrated circuit stack including a patterned array of electrically conductive pillars
The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer...
US-9,548,276 Structure of backside copper metallization for semiconductor devices and a fabrication method thereof
An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, wherein the improved structure comprises...
US-9,548,275 Detecting sudden changes in acceleration in semiconductor device or semiconductor packaging containing...
An approach for detecting sudden changes in acceleration in a semiconductor device or semiconductor package containing the semiconductor device is disclosed. In...
US-9,548,274 Reticle for non-rectangular die
The present disclosure provides a semiconductor structure. The semiconductor structure includes a non-rectangular die area, a dicing ring and a reticle area...
US-9,548,273 Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other...
Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated...
US-9,548,272 Semiconductor device, circuit substrate, and electronic device
A semiconductor device has a through electrode formed in a through hole which penetrates a Si substrate from one surface to the other surface of the Si...
US-9,548,271 Semiconductor package
A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first...
US-9,548,270 Electrical fuse with metal line migration
An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes...
US-9,548,269 Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects
Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an...
US-9,548,268 Semiconductor device having bilayer metal layer
A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first...
US-9,548,267 Three dimensional circuit including shielded inductor and method of forming same
The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three...
US-9,548,266 Semiconductor package with embedded capacitor and methods of manufacturing same
A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor...
US-9,548,265 Chip package and manufacturing method thereof
A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The...
US-9,548,264 High density organic bridge device and method
Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic...
US-9,548,263 Semiconductor device package for debugging and related fabrication methods
Electronic device packages and related fabrication methods are provided. An exemplary electronic device includes a semiconductor die having debug circuitry...
US-9,548,262 Method of manufacturing semiconductor package and semiconductor package
In a semiconductor package, surfaces of a die pad, a semiconductor element, a connecting member, and a lead are subjected to a surface treatment with a silane...
US-9,548,261 Lead frame and semiconductor device
A lead frame of high quality which can endure direct bonding to a semiconductor element, and a semiconductor device of high reliability which utilizing the lead...
US-9,548,260 Semiconductor devices including conductive plug
Semiconductor devices include a substrate having a target connection region; a conductive line having a first side wall spaced apart from the substrate by at...
US-9,548,259 Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device comprises forming a first layer on an impurity diffusion region in a semiconductor substrate by a selective...
US-9,548,258 Silicon-on-plastic semiconductor device and method of making the same
A semiconductor device that does not produce nonlinearities attributed to a high resistivity silicon handle interfaced with a dielectric region of a buried...
US-9,548,257 Semiconductor device structures comprising polycrystalline CVD diamond with improved near-substrate thermal...
A semiconductor device structure includes a layer of III-V compound semiconductor material, a layer of polycrystalline CVD diamond material, and an interface...
US-9,548,256 Heat spreader and method for forming
The present disclosure provides embodiments for a semiconductor structure including a heat spreader that includes a graphene grid having a first major surface...
US-9,548,255 IC package having non-horizontal die pad and flexible substrate therefor
An integrated circuit (IC) package has a base, side walls mechanically connected to the base, IC dies respectively mounted on inner surfaces of the side walls...
US-9,548,254 Packaged semiconductor chips with array
A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and...
US-9,548,253 Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device and a semiconductor device that is manufactured by the method. In the method of manufacturing a semiconductor...
US-9,548,252 Reworkable epoxy resin and curative blend for low thermal expansion applications
A curable composition including: an epoxy resin; and an amine curing component including: an aromatic amine curing agent; and a solubilizer including an...
US-9,548,251 Semiconductor interposer having a cavity for intra-interposer die
A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor...
US-9,548,250 Semiconductor device including self-aligned gate structure and improved gate spacer topography
A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate, and at least one metal gate stack formed on the...
US-9,548,249 Methods of performing fin cut etch processes for FinFET semiconductor devices and the resulting devices
A method includes forming a plurality of fins above a substrate. A first mask layer is formed above a first subset of the fins. First portions of the fins in...
US-9,548,248 Method of processing a substrate and a method of processing a wafer
According to various embodiments, a method of processing a substrate may include: forming a plurality of trenches into a substrate between two chip structures...
US-9,548,247 Methods for producing semiconductor devices
A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first...
US-9,548,246 Substrate dividing method
A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method...
US-9,548,245 Isolation rings for packages and the method of forming the same
A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is...
US-9,548,244 Self-aligned contact structure
Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first...
US-9,548,243 Self aligned via and pillar cut for at least a self aligned double pitch
A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an...
US-9,548,242 Nanoscale interconnects fabricated by electrical field directed assembly of nanoelements
The invention provides a fast, scalable, room temperature process for fabricating metallic nanorods from nanoparticles or fabricating metallic or semiconducting...
US-9,548,241 Semiconductor device metallization systems and methods
Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a...
US-9,548,240 Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive...
US-9,548,239 Method for fabricating contact plug in an interlayer dielectric layer
A gate structure is first formed on a substrate and an interlayer dielectric (ILD) layer is formed around the gate structure, a dielectric layer is formed on...
US-9,548,238 Method of manufacturing a semiconductor device using a self-aligned OPL replacement contact and patterned HSQ...
A method for manufacturing a semiconductor device, comprises forming an organic planarization layer on a plurality of gates on a substrate, wherein the...
US-9,548,237 Method for transferring a layer comprising a compressive stress layer and related structures
A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to...
US-9,548,236 Methods of forming strained-semiconductor-on-insulator device structures
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
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