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Patent # Description
US-9,548,135 Method and apparatus for determining status element total with sequentially coupled counting status circuits
Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a...
US-9,548,134 Semiconductor integrated circuit device and multi chip package including the same
A semiconductor integrated circuit device includes a first circuit block configured to receive data from a plurality of data I/O (input/output) lines and output...
US-9,548,133 Shift register circuit
A shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an...
US-9,548,132 Shift register memory device, shift register, and data storage method
According to one embodiment, a shift register memory device includes a shift register, a program/read element, and a rotating force application unit. The shift...
US-9,548,131 Reduced power read sensing for one-time programmable memories
A low power consuming read circuit for a memory array is disclosed. The circuit is particularly useful in applications where oxide breakdown one-time...
US-9,548,130 Non-volatile memory with prior state sensing
A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication...
US-9,548,129 Word line look ahead read for word line to word line short detection
Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example...
US-9,548,128 Read retry for non-volatile memories
An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a...
US-9,548,127 Memory system
According to one embodiment, a memory system includes: a semiconductor memory device and a controller. The semiconductor memory device reads data a plurality of...
US-9,548,126 Multi-chip non-volatile semiconductor memory package including heater and sensor elements
A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a...
US-9,548,125 Semiconductor device having multi-level cell and method of reading the same
A semiconductor device and a method of operating the same are provided. The method includes determining whether a read operation on a selected page is a...
US-9,548,124 Word line dependent programming in a memory device
A memory device includes memory cells arranged in word lines. Due to variations in the fabrication process, with width and spacing between word lines can vary,...
US-9,548,123 Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy...
A nonvolatile memory device includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory...
US-9,548,122 Level shift driver circuit capable of reducing gate-induced drain leakage current
A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second P-type transistors and a...
US-9,548,121 Memory device having only the top poly cut
Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory...
US-9,548,120 Content addressable memory
Content addressable memory (CAM) devices provide for high density, low cost CAM devices. CAM devices include a non-volatile memory array having a plurality of...
US-9,548,119 Memory device comprising an electrically floating body transistor
A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI)...
US-9,548,118 Method, system and device for complementary non-volatile memory device operation
Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in...
US-9,548,117 Non-volatile SRAM with multiple storage states
Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the...
US-9,548,116 Resistive memory with program verify and erase verify capability
A resistive non-volatile memory cell is programmed. A programming voltage is applied to a first terminal of the resistive non-volatile memory cell. Sensing,...
US-9,548,115 Variable resistance element, semiconductor device having variable resistance element, semiconductor device...
This variable resistance element is provided with a variable resistance film, a first electrode, which is disposed in contact with one surface of the variable...
US-9,548,114 Resistive semiconductor memory capable of performing incremental step pulse programming (ISPP) based on digital...
Disclosed are a semiconductor memory apparatus, a program method, and a program system. The semiconductor memory apparatus includes a memory cell array...
US-9,548,113 Tamper-resistant non-volatile memory device
A non-volatile memory device includes a memory cell array including memory cells, a read circuit that, in operation, obtains pieces of resistance value...
US-9,548,112 Semiconductor device and information reading method
A semiconductor device including a memory device configured to take a plurality of resistance states that are distinguishable from one another; a bias...
US-9,548,111 Memory device
According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second...
US-9,548,110 Memory device and method for thermoelectric heat confinement
A memory device for thermoelectric heat confinement and method for producing same. The memory device includes a plurality of phase-change memory cells, wherein...
US-9,548,109 Circuit and system of using FinFET for building programmable resistive devices
Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a...
US-9,548,108 Virtual memory device (VMD) application/driver for enhanced flash endurance
A Virtual-Memory Device (VMD) driver and application execute on a host to increase endurance of flash memory attached to a Super Enhanced Endurance Device...
US-9,548,107 Semiconductor memory device
A semiconductor memory device includes a memory cell configured to hold 4-bit data according to a threshold. A first bit of the 4-bit data is established by...
US-9,548,106 Semiconductor storage device
A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural...
US-9,548,105 Enhanced post-write read for 3-D memory
Apparatus and method for performing a post-write read in a memory device are disclosed. A memory device may include 3-dimensional memory, with the wordlines in...
US-9,548,104 Boost control to improve SRAM write operation
Approaches for providing write-assist boost for a Static Random Access Memory (SRAM) array are provided. A circuit includes a write driver of a Static Random...
US-9,548,103 Scaleable look-up table based memory
An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory...
US-9,548,102 Multi-die DRAM banks arrangement and wiring
The various embodiments described herein include memory dies and methods for memory die communications. In one aspect, a method is performed at a first memory...
US-9,548,101 Retention optimized memory device using predictive data inversion
A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory...
US-9,548,100 Semiconductor memory apparatus performing a refresh operation
A semiconductor memory apparatus may include a refresh mode control circuit configured to enable a row address increase signal when all banks capable of being...
US-9,548,099 Memory device with advanced refresh scheme
A memory device includes a counter suitable for counting the number of times that a periodic wave is enabled and generating a code, one or more memory banks...
US-9,548,098 Non-destructive write/read leveling
In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may...
US-9,548,097 Magnetic random access memory
According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements,...
US-9,548,096 Reverse complement magnetic tunnel junction (MTJ) bit cells employing shared source lines, and related methods
Reverse complement MTJ bit cells employing shared source lines are disclosed. In one aspect, a 2T2MTJ reverse complement bit cell employing shared source line...
US-9,548,095 Redundant magnetic tunnel junctions in magnetoresistive memory
Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory...
US-9,548,094 Magnetic random access memory cell with a dual junction for ternary content addressable memory applications
A MRAM cell including a first tunnel barrier layer between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a...
US-9,548,093 Magnetic memory element and magnetic memory
A magnetic memory element includes a first magnetic unit, a second magnetic unit, a third magnetic unit, a read/write unit, a first electrode, a second...
US-9,548,092 Voltage controlled spin transport channel
A spin transport channel includes a dielectric layer contacting a conductive layer. The dielectric layer includes at least one of a tantalum oxide, hafnium...
US-9,548,091 Memory module having address mirroring function
A memory module having an address mirroring function is provided. The memory module includes a register that allows mode registers of first memory chips of a...
US-9,548,090 Adjustment method of signal level in semiconductor device and semiconductor device
Characteristics of each transistor in a semiconductor device including a transistor of a memory cell are measured by an ASV monitoring circuit, a power supply...
US-9,548,089 Pipelining an asynchronous memory reusing a sense amp and an output latch
An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit...
US-9,548,088 Semiconductor memory asynchronous pipeline
An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data...
US-9,548,087 Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features
Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages....
US-9,548,086 Integrated circuit device body bias circuits and methods
A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein,...
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