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Patent # Description
US-9,553,132 Semiconductor memory device
According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory...
US-9,553,131 Semiconductor device and forming method
Disclosed is a semiconductor device that reduces the area of a transistor in a ReRAM. A plurality of memory cells differ from each other in the combination of...
US-9,553,130 Semiconductor device and method for producing a semiconductor device
A semiconductor device includes four or more memory cells arranged on a row, the memory cells each including a first pillar-shaped semiconductor layer, a first...
US-9,553,129 Magnetic tunnel junction stack alignment scheme
Device and methods of forming a device are disclosed. The method includes providing a substrate defined with a memory cell region. A first upper dielectric...
US-9,553,128 Linear MRAM device with a self-aligned bottom contact
A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel...
US-9,553,127 LED array
A light-emitting diode structure comprises a first epitaxial unit; a second epitaxial unit separated from the first epitaxial unit; a crossover metal layer...
US-9,553,126 Wafer-level bonding method for camera fabrication
A wafer-level method for fabricating a plurality of cameras includes modifying an image sensor wafer to reduce risk of the image sensor wafer warping, and...
US-9,553,125 Solid-state imaging device, manufacturing method thereof, and electronic apparatus
Disclosed is a solid-state imaging device including: a solid-state imaging element which outputs an image signal according to an amount of light sensed on a...
US-9,553,124 CMOS image sensor with sigma-delta type analog-to-digital conversion
A CMOS image sensor including a plurality of pixels, each including: a photodiode; a sigma-delta modulator of order p, p being an integer greater than or equal...
US-9,553,123 Back-illuminated sensor chips
A back-illuminated sensor chip is disclosed, which includes one or more pixel areas each including a plurality of pixels located in a plane and arranged in a...
US-9,553,122 Backside illuminated image sensor
A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer...
US-9,553,121 Semiconductor device and method of manufacturing the same
A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier...
US-9,553,120 Image sensor using backside illumination photodiode and method for manufacturing the same
A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside...
US-9,553,119 Methods of forming an image sensor
Methods of forming an image sensor are provided. A method of forming an image sensor includes forming a trench in a substrate to define a unit pixel region of...
US-9,553,118 Formation of buried color filters in a back side illuminated image sensor using an etching-stop layer
A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed...
US-9,553,117 Solid-state image pickup apparatus, and image pickup system using solid-state image pickup apparatus
A solid-state image pickup apparatus includes a photoelectric conversion unit, a charge storage unit, and a floating diffusion unit, all disposed on a...
US-9,553,116 Imaging detector having an integrated wide bandgap layer and method of manufacturing thereof
A substrate-removed, surface passivated, and anti-reflective (AR) coated detector assembly is provided. The assembly has an AR coating or passivation layer...
US-9,553,115 Manufacturing method of TFT substrate structure
The present invention provides a manufacturing method of a TFT substrate structure, which includes sequentially forming a first passivation layer, a...
US-9,553,114 Display device and electronic device with a color filter
A novel display device capable of adjusting color purity is provided. A novel display device with improved adhesion of a color filter is provided. A novel...
US-9,553,113 Pixel unit and pixel array
A pixel unit includes a scan line, data lines, first and second pixel structures, first and second common electrode lines, and a common connecting portion. The...
US-9,553,112 Array substrate and method of manufacturing the same, display panel and method of manufacturing the same, and...
The invention discloses an array substrate, a display panel and methods of manufacturing the same, and a display device. The array substrate comprises: a pixel...
US-9,553,111 Thin film transistor array substrate
A pixel electrode of an array substrate is connected with a drain electrode of a TFT via a first aperture formed on a second interlayer insulating film, a...
US-9,553,110 Array substrate, display device and method of manufacturing the array substrate
An array substrate, a display device comprising the array substrate and a method of manufacturing the array substrate are provided. The array substrate include...
US-9,553,109 Thin film transistor substrate, method for manufacturing the same, and liquid crystal display
A thin film transistor substrate includes a semiconductor channel layer made of an oxide semiconductor, protective insulating layers that cover the...
US-9,553,108 Array substrate, method of manufacturing the same and display device
The present invention discloses an array substrate, a method of manufacturing the array substrate and a display device. Since the respective surfaces of the...
US-9,553,107 Shallow extension junction
A method for fabricating a semiconductor device includes receiving a finned substrate comprising an isolation layer with a plurality of semiconductor fins...
US-9,553,106 Three-dimensional nonvolatile memory device
A three-dimensional nonvolatile memory device includes a substrate defined with a slimming region, first and second pass regions on both sides of the slimming...
US-9,553,105 Semiconductor devices including gate insulation layers on channel materials
Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device...
US-9,553,104 Semiconductor device and method of fabricating the same
Provided is a fabricating method of a semiconductor device, including the following. Fin structures are formed on a substrate, and the adjacent fin structures...
US-9,553,103 Memory cell profiles
Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from...
US-9,553,102 Tungsten separation
Methods of selectively etching tungsten from the surface of a patterned substrate are described. The etch electrically separates vertically arranged tungsten...
US-9,553,101 Semiconductor device
A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode...
US-9,553,100 Selective floating gate semiconductor material deposition in a three-dimensional memory structure
A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a...
US-9,553,099 Pillar arrangement in NAND memory
Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the...
US-9,553,098 Semiconductor devices including separate line patterns
A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on...
US-9,553,097 Semiconductor device, related manufacturing method, and related electronic device
A semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor includes a first source terminal formed of a...
US-9,553,096 Semiconductor arrangement with capacitor
A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory...
US-9,553,095 Capacitor and method for making same
A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor...
US-9,553,094 Semiconductor device and method for fabricating the same
Provided is a method for fabricating a semiconductor device. The method includes forming an interlayer insulating layer on a substrate, the interlayer...
US-9,553,093 Spacer for dual epi CMOS devices
Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first...
US-9,553,092 Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs
Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different...
US-9,553,091 Semiconductor structure and method for manufacturing the same
A semiconductor structure is provided, which includes a first high-voltage MOS device region having a first well and a first light-doping region in a part of...
US-9,553,090 Structure and formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a...
US-9,553,089 Semiconductor device
A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns;...
US-9,553,088 Forming semiconductor device with close ground rules
A method for fabricating a semiconductor device comprises forming active regions on a semiconductor substrate, forming a gate stack over the active regions and...
US-9,553,087 Semiconductor device
In some embodiments, a semiconductor device includes a first transistor and a second transistor. The first transistor includes a first source region in a first...
US-9,553,086 Reverse-conducting semiconductor device
A Reverse-conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer...
US-9,553,085 Fabricating method for high voltage semiconductor power switching device
A three terminal high voltage Darlington bipolar transistor power switching device includes two high voltage bipolar transistors, with collectors connected...
US-9,553,084 Switching element, semiconductor device, and semiconductor device manufacturing method
According to the present invention, a switching element includes a substrate, a first gate pad formed on the substrate, a second gate pad formed on the...
US-9,553,083 Apparatus for controlling heat flow
An apparatus configured to control a heat flow is provided. The apparatus may include a semiconductor device region formed in a matrix; a heat rectifier region...
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