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Patent # Description
US-9,553,082 Process for improving critical dimension uniformity of integrated circuit arrays
Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In...
US-9,553,081 Semiconductor device including a redistribution layer and metallic pillars coupled thereto
A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal...
US-9,553,080 Method and process for integration of TSV-middle in 3D IC stacks
Methods for integrating MOL TSVs in 3D SoC devices including face-to-face bonded IC chips. Embodiments include providing a device layer in each of IC chips on...
US-9,553,079 Flip chip assembly with connected component
A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A...
US-9,553,078 Light-emitting diode module and motor vehicle headlight
A light-emitting diode module includes a carrier and a plurality of optoelectronic semiconductor chips mounted on a carrier top and configured to generate...
US-9,553,077 LED module and method of manufacturing the same
A compact LED module and a method of manufacturing such an LED module are provided. The LED module includes a first-pole first lead, a first-pole second lead, a...
US-9,553,076 Stackable molded microelectronic packages with area array unit connectors
A microelectronic package having a substrate, a microelectronic element, e.g., a chip, and terminals can have conductive elements electrically connected with...
US-9,553,075 Recessed and embedded die coreless package
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a...
US-9,553,074 Semiconductor package having cascaded chip stack
A semiconductor package that includes a package substrate, a lower semiconductor chip mounted on the package substrate, and an upper semiconductor chip stacked...
US-9,553,073 Chip stack structure using conductive film bridge adhesive technology
A chip stack structure using conductive film bridge adhesive technology comprises a substrate, a first chip, at least one bridge element, a conductive film, and...
US-9,553,072 Semiconductor device package and method of manufacturing the same
A semiconductor device package includes a substrate, electrical components disposed on the substrate, and a conductive frame disposed on the substrate. The...
US-9,553,071 Multi-chip package with interconnects extending through logic chip
A microelectronic package includes a first microelectronic element comprising logic circuitry which is flip-chip mounted to a substrate, the substrate having...
US-9,553,070 3D packages and methods for forming the same
Embodiments of the present disclosure include a semiconductor device, a package, and methods of forming a semiconductor device and a package. An embodiment is a...
US-9,553,069 Bonding apparatus and substrate manufacturing equipment including the same
A bonding apparatus of substrate manufacturing equipment includes an upper stage, a lower stage facing the upper stage and which is configure and dedicated to...
US-9,553,068 Integrated circuit ("IC") assembly includes an IC die with a top metallization layer and a conductive epoxy...
An integrated circuit ("IC") assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end...
US-9,553,067 Semiconductor device
A semiconductor device includes a semiconductor layer, an electrode layer arranged on the semiconductor layer, a crack starting point layer arranged above the...
US-9,553,066 Post passivation interconnect structures and methods for forming the same
A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A...
US-9,553,065 Bumps for chip scale packaging including under bump metal structures with different diameters
A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is...
US-9,553,064 Electronic device, and manufacturing method of electronic device
An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings...
US-9,553,063 Semiconductor element, semiconductor device and method for manufacturing semiconductor element
The semiconductor element has an electrode including: a Ni-inclusion metal layer containing nickel formed on a side of at least one surface of the...
US-9,553,062 Fingerprint identification device
A fingerprint identification device includes a first dielectric layer, a fingerprint sensing chip, a packaging layer, a first redistribution layer, a second...
US-9,553,061 Wiring bond pad structures
The present disclosure relates to semiconductor structures and, more particularly, to wire bond pad structures and methods of manufacture. The structure...
US-9,553,060 Semiconductor device and manufacturing method therefor
Provided are a semiconductor device and a manufacturing method therefor that can prevent electric short-circuiting between redistribution lines. A barrier film...
US-9,553,059 Backside redistribution layer (RDL) structure
An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding...
US-9,553,058 Wafer backside redistribution layer warpage control
A method of forming a network of RDL lines on the backside of a thinned TSV die to control warpage and the resulting device are provided. Embodiments include...
US-9,553,057 E-plane probe with stepped surface profile for high-frequency
A method of forming an E-plane probe includes forming a plurality of monolithically integrated circuits (MICs) on a wafer, each MIC including a monolithic...
US-9,553,056 Semiconductor chip having tampering feature
Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device...
US-9,553,055 Method for fabricating semiconductor devices having reinforcing elements
The present disclosure provides a method for fabricating semiconductor devices having reinforcing elements. The method includes steps of providing a first wafer...
US-9,553,054 Strain detection structures for bonded wafers and chips
Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring...
US-9,553,053 Bump structure for yield improvement
A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and...
US-9,553,052 Magnetic shielding package of non-volatile magnetic memory element
A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer...
US-9,553,051 Electronic component
In an embodiment, an electronic component includes a dielectric layer having a first surface and a second surface, one or more semiconductor dies embedded in...
US-9,553,050 Semiconductor device
A semiconductor device includes a semiconductor substrate, an interlayer insulating film on the semiconductor substrate and having a first hole extending...
US-9,553,049 Copper interconnects having a titanium-platinum-titanium assembly between copper and compound semiconductor
Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a...
US-9,553,048 Semiconductor device and manufacturing method of semiconductor device
According to one embodiment, in a semiconductor device, a second contact is disposed at a position that is shifted from a first contact by a distance...
US-9,553,047 Method of manufacturing semiconductor devices with combined array and periphery patterning in self-aligned...
Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the patterning of...
US-9,553,046 E-fuse in SOI configuration
A method of forming a semiconductor device comprising a fuse is provided including providing a semiconductor-on-insulator (SOI) structure comprising an...
US-9,553,045 Inductor for post passivation interconnect and a method of forming
An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect...
US-9,553,044 Electrically conductive interconnect including via having increased contact surface area
An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis...
US-9,553,043 Interconnect structure having smaller transition layer via
An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom...
US-9,553,042 Semiconductor device and manufacturing method therefor
A wiring structure thereof includes a first interlayer insulating film, a first wiring and a first electrode for the capacitive element embedded in the first...
US-9,553,041 Semiconductor device package and manufacturing method thereof
Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of...
US-9,553,040 Semiconductor package
The invention provides a semiconductor package. The semiconductor package includes a semiconductor package includes a substrate having a die attach surface. A...
US-9,553,039 Semiconductor device with through-substrate via covered by a solder ball and related method of production
The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of...
US-9,553,038 Semiconductor cooling apparatus
An apparatus for cooling semiconductor elements uses heat exchangers to transfer heat from the semiconductor elements to a coolant flowing through the heat...
US-9,553,037 Semiconductor device
A semiconductor device includes a semiconductor element having a front surface and a rear surface, a pair of heat sinks disposed facing each other so as to...
US-9,553,036 Semiconductor package and manufacturing method thereof
A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided....
US-9,553,034 Combined semiconductor metrology system
A semiconductor wafer inspection system includes a camera and two or more illuminators. The illuminators illuminate a line of the semiconductor wafer in...
US-9,553,033 Semiconductor device models including re-usable sub-structures
Methods and tools for generating measurement models of complex device structures based on re-useable, parametric models are presented. Metrology systems...
US-9,553,032 Fin field effect transistor including asymmetric raised active regions
Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited...
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