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Patent # Description
US-9,553,031 Method for integrating germanides in high performance integrated circuits
A method for making an integrated circuit includes a) providing a substrate including n-type metal oxide semiconductor field effect transistors (NMOSFETs) and...
US-9,553,030 Method of manufacturing P-channel FET device with SiGe channel
A method of forming a semiconductor device is provided including providing a semiconductor-on-insulator (SOI) wafer comprising a first semiconductor layer...
US-9,553,029 Integrated circuit having a vertical power MOS transistor
A method includes forming a buried layer in a substrate, growing an epitaxial layer over the substrate, etching the epitaxial layer and the buried layer to form...
US-9,553,028 Methods of forming reduced resistance local interconnect structures and the resulting devices
A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial...
US-9,553,027 Fine patterning methods and methods of fabricating semiconductor devices using the same
A fine-patterning method includes forming a mask layer with lower and upper mask layers on an underlying layer, forming a pair of sacrificial patterns on the...
US-9,553,026 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first mandrel, a second mandrel, a third mandrel, and a fourth...
US-9,553,025 Selective Fin-shaping process
A method of forming a fin field-effect transistor (FinFET) includes forming a plurality of fins on a substrate. The method further includes forming an oxide...
US-9,553,024 Method of manufacturing semiconductor device
Object is to provide a semiconductor device having improved reliability or performance. A high-breakdown-voltage n type transistor has source and drain regions...
US-9,553,023 Substrate dividing method
A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method...
US-9,553,022 Method for use in manufacturing a semiconductor device die
In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are...
US-9,553,021 Method for processing a wafer and method for dicing a wafer
In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed...
US-9,553,020 Interconnect structure for connecting dies and methods of forming the same
A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first...
US-9,553,019 Airgap protection layer for via alignment
A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first...
US-9,553,018 Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects
Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an...
US-9,553,017 Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal...
US-9,553,016 Contacts for semiconductor devices and methods of forming thereof
A method for a method of forming a semiconductor device includes providing a semiconductor substrate having a bottom surface opposite a top surface with...
US-9,553,015 Fabrication of III-V-on-insulator platforms for semiconductor devices
Embodiments of the present invention provide III-V-on-insulator (IIIVOI) platforms for semiconductor devices and methods for fabricating the same. According to...
US-9,553,014 Bonded processed semiconductor structures and carriers
Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or...
US-9,553,013 Semiconductor structure with TRL and handle wafer cavities
A method is disclosed. The method comprises fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate. The device layer...
US-9,553,012 Semiconductor structure and the manufacturing method thereof
The present disclosure provides a FinFET. The FinFET includes a silicon-on-insulator (SOI) with an insulator; a plurality of fin structures on the insulator; an...
US-9,553,011 Deep trench isolation with tank contact grounding
An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite,...
US-9,553,010 Wafer gripper with non-contact support platform
A wafer transport system includes a substantially horizontal non-contact support platform for supporting a wafer substantially horizontally at a substantially...
US-9,553,009 Substrate separation device and substrate separation system
There is provided a substrate separation device and method for separating a growth substrate from a laminate structure which includes a support substrate, a...
US-9,553,008 Methods to reduce debonding forces on flexible semiconductor films disposed on vapor-releasing adhesives
A method comprises providing a handle substrate having a front surface and a back surface; providing a layer of flexible semiconductor material having a front...
US-9,553,007 Coating method and coating apparatus
A coating method includes a step of forming a film of a coating solution having a larger thickness in a central region of a substrate than in an edge region of...
US-9,553,006 High definition heater system having a fluid medium
An apparatus, such as a heater, is provided that includes a base member having at least one fluid passageway. A two-phase fluid is disposed within the fluid...
US-9,553,005 Metal liftoff tools and methods
In certain embodiments the metal liftoff tool comprises an immersion tank for receiving a wafer cassette with wafers therein, the immersion tank including an...
US-9,553,004 Cleaning method
To provide a cleaning method which makes it possible to reduce alkaline component mixing in an ozone cleaning solution, thereby preventing impairment of...
US-9,553,003 Substrate processing device and substrate processing method
In a substrate processing device 10 having a heating and drying unit 103 for drying a surface of a substrate W, the heating and drying unit 103 heats upward a...
US-9,553,002 Flow controlled liner having spatially distributed gas passages
Embodiments of the present disclosure provide a liner assembly including a plurality of individually separated gas passages. The liner assembly enables...
US-9,553,001 Method of forming a molding layer for semiconductor package
A method of forming a molding layer includes the following operations: forming a substrate having at least one column structure thereon; flipping over the...
US-9,553,000 Interconnect structure for wafer level package
A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation...
US-9,552,999 Packaged electronic device having reduced parasitic effects and method
In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip...
US-9,552,998 Thin film transistor, method of manufacturing thin film transistor and flat panel display having the thin film...
A thin film transistor (TFT), method of manufacturing the TFT and a flat panel display having the TFT are disclosed. In one aspect, the TFT comprises a...
US-9,552,997 Silicon carbide switching devices including P-type channels
Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to...
US-9,552,996 Semiconductor device, having conductive pattern and electronic apparatus
There is provided a conductive pattern forming method that can suppress shape abnormalities caused by the reattachment of a neodymium component. A conductive...
US-9,552,995 Electrical interconnect for an electronic package
Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a...
US-9,552,994 Plating apparatus, plating method, and storage medium
A plating apparatus 20 includes a substrate holding device 110 configured to hold and rotate the substrate 2; a first discharge device 30 configured to...
US-9,552,993 Semiconductor device and manufacturing method thereof
A number of variations may include a method that may include depositing a first layer on a first semiconductor epi layer (epitaxial layer) in an overlying...
US-9,552,992 Co-fabrication of non-planar semiconductor devices having different threshold voltages
Co-fabricating non-planar (i.e., three-dimensional) semiconductor devices with different threshold voltages includes providing a starting semiconductor...
US-9,552,991 Trench vertical NAND and method of making thereof
A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers...
US-9,552,990 Storage and sub-atmospheric delivery of dopant compositions for carbon ion implantation
A supply source for delivery of a CO-containing dopant gas composition is provided. The composition includes a controlled amount of a diluent gas mixture such...
US-9,552,989 Apparatus and method for improved control of heating and cooling of substrates
Methods and apparatus for processing substrates and controlling the heating and cooling of substrates are described. A radiation source providing radiation in a...
US-9,552,988 Tone inverted directed self-assembly (DSA) fin patterning
A method for DSA fin patterning includes forming a BCP layer over a lithographic stack, the BCP layer having first and second blocks, the lithographic stack...
US-9,552,987 Substrate processing method, substrate processing apparatus, and storage medium
A substrate processing method is performed to improve surface roughness of a pattern mask formed on a substrate by being exposed and developed. The method...
US-9,552,986 Forming a memory device using sputtering to deposit silver-selenide film
A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The...
US-9,552,985 Oxide semiconductor layer and production method therefor, oxide semiconductor precursor, oxide semiconductor...
The invention provides an oxide semiconductor layer that has less cracks and is excellent in electrical property and stability, as well as a semiconductor...
US-9,552,984 Processing method of substrate and manufacturing method of liquid ejection head
There are provided a processing method of a substrate in which in forming a trench on the substrate by etching, a side wall surrounding the trench is surely...
US-9,552,983 Manufacturing method for semiconductor device
A manufacturing method for a semiconductor device, including: loading a wafer into a reaction chamber; placing the wafer on a push-up shaft moved up; preheating...
US-9,552,982 Apparatuses and methods for depositing SiC/SiCN films via cross-metathesis reactions with organometallic...
Disclosed herein are methods of forming SiC/SiCN film layers on surfaces of semiconductor substrates. The methods may include introducing a silicon-containing...
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