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Patent # Description
US-9,552,880 Screening for later life stuck bits in ferroelectric memories
A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high...
US-9,552,879 Nonvolatile memory device having variable resistance memory cells and a method of resetting by initially...
A method of resetting a variable resistance memory cell in a nonvolatile memory device includes; programming the memory cell to a set state using a...
US-9,552,878 Resistive memory device and operating method
A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line...
US-9,552,877 Writable device based on alternating current
A nonvolatile memory device is writable to a high resistance state and a low resistance state. The nonvolatile memory device may be heated to at least a...
US-9,552,876 Descending set verify for phase change memory
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
US-9,552,875 Apparatuses and methods for sensing using an integration component
The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a...
US-9,552,874 Combined memory block and data processing system having the same
A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit,...
US-9,552,873 Memory device
A device includes memory cells, reference memory cells, and a sensing unit. The reference memory cells are configured to store first bit data, second bit data,...
US-9,552,872 Memory device
Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node...
US-9,552,871 Low power high performance electrical circuits
Hybrid Super Threshold (SupVt) circuits are CMOS circuits that can function in two different operation modes: a normal operation mode and a SupVt power saving...
US-9,552,870 Memory includes transmitter for data synchronization transmission after a mode switch and method thereof
An apparatus includes a memory and a circuit. The memory may have a transmitter. The memory may be configured to (a) train transmit parameters of the...
US-9,552,869 Random access memory with pseudo-differential sensing
Embodiments herein describe DRAM that includes storage circuitry coupled between complementary bit lines which are in turn coupled to the same sense amplifier....
US-9,552,868 Semiconductor memory device having various column repair modes
A memory device including first to fourth cell blocks, each including a plurality of normal columns and one or more redundancy columns and a control unit...
US-9,552,867 Semiconductor memory devices and memory systems including the same
A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes...
US-9,552,866 Semiconductor device including subword driver circuit
The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or...
US-9,552,865 Method and apparatus for calibrating write timing in a memory system
A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller...
US-9,552,864 Offset compensation for ferroelectric memory cell sensing
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g.,...
US-9,552,863 Memory device with sampled resistance controlled write voltages
A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a...
US-9,552,862 Magnetic ram array architecture
A magnetic random access memory (MRAM) array including: a plurality of MRAM cells arranged in an array configuration, each comprising a first type nTron and a...
US-9,552,861 Resistance change memory
A first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first...
US-9,552,860 Magnetic memory cell structure with spin device elements and method of operating the same
A magnetic memory includes a plurality of memory cells and a data identification circuit. Each of the memory cells includes: a first bias node to which a first...
US-9,552,859 Electronic memory including ROM and RAM
An electronic data-storage apparatus having ROM embedded in an STT-MRAM. The apparatus comprises at least two bit lines, a plurality of bit cells, each...
US-9,552,858 STT-MRAM cell structure incorporating piezoelectric stress material
A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the...
US-9,552,857 Address generation circuit and semiconductor memory device including the same
An address generation circuit includes: a first address control clock generation unit suitable for generating a first address control clock signal in response...
US-9,552,856 Memory timing self-calibration
Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes...
US-9,552,855 Accessing a serial number of a removable non-volatile memory device
A removable non-volatile memory device durably stores a serial number or identifier, which is used to mark multimedia content legally stored on the removable...
US-9,552,854 Register files including distributed capacitor circuit blocks
Some embodiments include apparatuses having a first node to receive a supply voltage, a second node, a switching circuit to couple the first node to the second...
US-9,552,853 Methods for calibrating a read data path for a memory interface
A method for calibrating a read data path for a DDR memory interface circuit from time to time in conjunction with functional operation of a memory circuit is...
US-9,552,852 Doped metal-insulator-transition latch circuitry
Some embodiments of the present invention may include one, or more, of the following features, characteristics or advantages: (i) latch device including...
US-9,552,851 Current-mode sense amplifier
A current sense amplifier comprises a reference current input terminal, a control line input terminal, a sense current input terminal, an output terminal, a...
US-9,552,850 Sense amplifier driving device and semiconductor device including the same
An embodiment relates to a sense amplifier driving device for stabilizing bit line precharge power when a post-overdriving operation is performed. The sense...
US-9,552,849 Memory device with timing overlap mode and precharge timing circuit
In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events...
US-9,552,848 Solid state drive with improved enclosure assembly
The present invention pertains to a hard disk drive form factor compatible solid-state storage device enclosure assembly that protects circuit boards contained...
US-9,552,847 Electronic device and covering structure
An electronic device including a metal casing and a covering structure is provided. The metal casing has a first opening. The covering structure includes a...
US-9,552,846 Variable speed data storage device testing system
A data storage device can be tested while spinning at a variety of different speeds. Data may be written to a data sector with a transducing head while at least...
US-9,552,845 Automatic generation of metadata for audio dominance effects
Metadata comprising a set of gain values for creating a dominance effect is automatically generated. Automatically generating the metadata includes receiving...
US-9,552,844 Image processing apparatus, image processing method and program
To easily edit dynamic image content suiting user's preferences in consideration of the geographical position. A trajectory information generation unit 230...
US-9,552,843 Media file access and storage solution for multi-workstation/multi-platform non-linear video editing systems
A novel system, method and computer program product for accessing digital media files stored in a media storage device via a server device in communication with...
US-9,552,842 Systems and methods for managing the process of creating custom professional videos
Systems and methods for creating custom professional videos are disclosed. The system includes client computing devices, an administrator computing device, and...
US-9,552,841 Magnetic tape servo format allowing for increased linear tape density and systems thereof
In one general embodiment, a magnetic recording tape includes a plurality of servo tracks, each servo track comprising a series of magnetically defined bars,...
US-9,552,840 Three-dimensional sound capturing and reproducing with multi-microphones
A method for audio signal processing is described. The method includes decomposing a recorded auditory scene into a first category of localizable sources and a...
US-9,552,839 Optical recording medium and manufacturing method of the same
Provided is an optical recording medium including: two discs, each of which includes a substrate and a plurality of recording layers; and an attachment layer...
US-9,552,838 Optical information recording medium having first and second pit row of identical reflectance
In a case where (i) a reflectance calculated from a reflected light amount obtained from a longest pit (P1max) or a longest space (S1max) in a first pit row is...
US-9,552,837 Vertically and horizontally weakly coupled perpendicular small grain media
In one general embodiment, a magnetic medium includes a recording layer having at least three exchange control layers each having a magnetic moment less than...
US-9,552,836 Slider including one or more fluid pathways, and related apparatuses and methods
The present invention is directed to a slider that includes at least one fluid pathway that is in fluid communication with an air bearing face and/or the...
US-9,552,835 Actuator limiters for multiple disk-stack, shared actuator hard disk drive
An actuator rotational limiter mechanism for a multiple disk-stack, shared actuator hard disk drive includes an actuator comb with a cam-lock feature and an...
US-9,552,834 Stabilization of one or more upper sensors in multi-sensor readers
A multi-sensor reader that includes a first sensor that has a first sensor stack, which includes a sensing layer that has a magnetization that changes according...
US-9,552,833 Devices including a multilayer gas barrier layer
Devices that include a near field transducer (NFT); a multilayer gas barrier layer positioned on at least a portion of the NFT, the multilayer gas barrier layer...
US-9,552,832 Read-write non-erasable memory with laser recording and method of recording
A nonvolatile memory comprising at least one ferromagnetic region having permeability which changes from a first state to a second state of lower permeability...
US-9,552,831 Method for detecting abnormal sound and method for judging abnormality in structure by use of detected value...
The present invention provides a method for obtaining an accurate detected value of a similarity, such as an hitting sound. The method includes the steps of:...
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