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Patent # Description
US-9,552,325 Camera control interface extension bus
System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control...
US-9,552,324 Dynamic data collection communication between adapter functions
An approach is provided that collects data from a multi-function adapter that is used by multiple functions. In the approach, a master function is dynamically...
US-9,552,323 High-speed peripheral component interconnect (PCIe) input-output devices with receive buffer management circuitry
Interface circuitry is provided to control the flow of data transmitted over a high-speed serial link. The interface circuitry may receive data over a...
US-9,552,322 Hybrid repeater for supporting backward compatibility
Hybrid repeaters are described that are capable of transmitting data in accordance with different versions of a serial data protocol are described. The...
US-9,552,321 Apparatus and method for automatically aligning data signals and strobe signals on a source synchronious bus
A method for aligning signals on a bus, including: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe;...
US-9,552,320 Source synchronous data strobe misalignment compensation mechanism
A method that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a...
US-9,552,319 System interconnect dynamic scaling handshake using spare bit-lane
A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic...
US-9,552,318 Removable memory card type detection systems and methods
Removable memory card type detection systems and methods are disclosed. In one aspect, a removable memory card is inserted into a receptacle of a host. The host...
US-9,552,317 Apparatus and method for operating and switching a single conductor interface
This application discusses, among other things, communication apparatus and methods, and more particularly, a single conductor or single wire communication...
US-9,552,316 Techniques for adaptive interface support
Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in...
US-9,552,315 Determining addresses of electrical components arranged in a daisy chain
In one aspect, a system includes electrical components arranged in a daisy chain that include a first electrical component disposed at a first end of the daisy...
US-9,552,314 Memory system having first and second memory devices and driving method thereof
A memory system includes first and second memory devices, a memory controller configured to control the second memory device, to store a request signal to...
US-9,552,313 Delivering real time interrupts with an advanced programmable interrupt controller
Embodiments of apparatuses and methods for delivering real time interrupts with an APIC are disclosed. In one embodiment, an apparatus includes a local advanced...
US-9,552,312 Executing virtual functions using memory-based data in a PCI express SR-IOV and MR-IOV environment
A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a...
US-9,552,311 Method for assigning addresses to memory devices
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an...
US-9,552,310 Signal control circuit, information processing apparatus, and signal control method
An EVEN component selecting unit and an ODD component selecting unit acquire a first signal from a DQ signal based on a rising edge of a DQS signal and a second...
US-9,552,309 Methods, systems, and computer readable media for providing precise timing in virtual data network or storage...
Methods, systems, and computer readable media for providing precise timing in a virtual data network or storage network test environment are provided. One...
US-9,552,308 Early wake-warn for clock gating control
A request associated with a particular cache record is generated to be sent to a system component associated with a cache bank over an interconnect. A wake-warn...
US-9,552,307 Information processing apparatus and computer program product
According to an embodiment, an information processing apparatus includes a secure OS, a non-secure OS, and a monitor. The monitor is configured to switch...
US-9,552,306 Concurrent virtual tape usage
A request to access a virtual tape volume is identified and a lock status is maintained for the virtual tape volume. The lock status includes a shared status...
US-9,552,305 Compacting dispersed storage space
A method begins by a processing module identifying a first storage space zone that includes a plurality of deleted encoded data slices and a plurality of active...
US-9,552,304 Maintaining command order of address translation cache misses and subsequent hits
A computer-implemented method includes storing commands and maintaining an order of receipt of the commands in a command processing unit. The commands include...
US-9,552,303 Method and system for maintaining release consistency in shared memory programming
A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in...
US-9,552,302 Data processing apparatus, data processing method and program recording medium
To enable moving and copying structured data as block data at high speed, and tracing the moved or copied structured data at high speed. A data processing...
US-9,552,301 Method and apparatus related to cache memory
A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache...
US-9,552,300 Cache system using solid state drive
A cache system for a storage device includes a solid state drive (SSD), a random access memory (RAM), and a cache control device. The cache control device is...
US-9,552,299 Systems and methods for rapid processing and storage of data
Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are...
US-9,552,298 Smart pre-fetch for sequential access on BTree
Methods and systems configured to facilitate smart pre-fetching for sequentially accessing tree structures such as balanced trees (b-trees) are described...
US-9,552,297 Method and apparatus for efficient cache read ahead
A method for providing improved sequential read performance in a storage controller is provided. In response to the storage controller receiving a host read...
US-9,552,296 Verifying shared memory integrity
A method, a system and a computer program product including instructions for verification of the integrity of a shared memory using in line coding is provided....
US-9,552,295 Performance and energy efficiency while using large pages
Technologies are described herein for improving performance and energy efficiency in a computing system while using a large memory page size. Some example...
US-9,552,294 Dynamically configuring regions of a main memory in a write-back mode or a write-through mode
The described embodiments include a main memory and a cache memory (or "cache") with a cache controller that includes a mode-setting mechanism. In some...
US-9,552,293 Emulating eviction data paths for invalidated instruction cache
A method of managing processor caches. The method includes invalidating a cache line from a first instruction cache level and in response to invalidating the...
US-9,552,292 Apparatus and method for allocating virtual memory addresses to continuous physical addresses
A storage management apparatus configured to allocate physical addresses in a physical storage area, to virtual addresses in a virtual storage area for storing...
US-9,552,291 Memory management method
A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a)...
US-9,552,290 Partial R-block recycling
An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the...
US-9,552,289 Bitwise addressing of entries in a forward lookup table
A logical address is received that references data stored at a physical address of a non-volatile memory. From the logical address, one or more words of a...
US-9,552,288 Multi-tiered memory with different metadata levels
Method and apparatus for managing data in a memory. In accordance with some embodiments, a data object is stored in a first non-volatile tier of a multi-tier...
US-9,552,287 Data management method, memory controller and embedded memory storage apparatus using the same
A data management method, a memory controller and an embedded memory storage apparatus are provided. The embedded memory storage apparatus has a plurality of...
US-9,552,286 Information processing apparatus and installation method
The installation of multiple applications by an installer is executed in a mode that does not display an error message in a display device. Upon an installation...
US-9,552,285 Micro-execution for software testing
Micro-execution is the ability to run any code segment in isolation. Implementations for micro-execution of code segments are described. A test engine...
US-9,552,284 Determining valid inputs for an unknown binary program
A method to determine valid input sequences for an unknown binary program is provided. The method includes obtaining multiple input sequences, which each...
US-9,552,283 Spreadsheet data transfer objects
Various systems and methods are disclosed for automatically generating a spreadsheet template to store information usable to generate one or more data transfer...
US-9,552,282 Module interrogation
Module interrogation techniques are described in which modules configured to rely upon one or more operating system features are interrogated to determine which...
US-9,552,281 Utilizing a test automation tool in a test automation environment
Systems and methods are disclosed for integrating JAVA objects, such as handlers, into a scripting language to be used as part of a test automation environment...
US-9,552,280 Visual analysis and debugging of complex event flows
Methods, systems, and computer-readable media to generate a user interface (UI) to analyze a complex event processing (CEP) query are disclosed. A particular...
US-9,552,279 Data bus network interface module and method therefor
A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated...
US-9,552,278 Configurable code fingerprint
A method, computer program product, and system performing a method that include a processor defining a code fingerprint by obtaining parameters describing at...
US-9,552,277 Synchronized java debugger
A synchronized JAVA debugger maintains synchronization between a JAVA source file in the debugger current working directory and a corresponding JAVA stored...
US-9,552,276 Query-based software dependency analysis
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generated aggregated dependencies between software elements...
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