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Patent # Description
US-9,559,132 Solid-state image capture device
A semiconductor substrate is provided with a plurality of photosensitive regions on a first principal surface side. An insulating film has a third principal...
US-9,559,131 Solid-state imaging device and method for manufacturing solid-state imaging device, and electronic device
A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor...
US-9,559,130 Depth sensing pixel, composite pixel image sensor and method of making the composite pixel image sensor
A method of making a composite pixel image sensor includes forming an image sensing array; and forming a depth sensing pixel. The depth sensing pixel includes a...
US-9,559,129 Semiconductor device having antenna and method for manufacturing thereof
The present invention provides an antenna in that the adhesive intensity of a conductive body formed on a base film is increased, and a semiconductor device...
US-9,559,128 Pad structure and display device having the same
The present disclosure provides a pad structure and associated display device. The pad structure comprises: a plurality of line on glass (LOG) lines that are...
US-9,559,127 Thin film transistor array panel
A thin film transistor array panel includes an insulation substrate; a gate line and a first electrode on the insulation substrate; a gate insulating layer on...
US-9,559,126 Array substrate and display device
An array substrate and a display including the array substrate, the array substrate includes a substrate (1); a pixel structural layer formed on the substrate...
US-9,559,125 Array substrate, display device, and method for manufacturing the array substrate
An array substrate includes a substrate and data lines and scan lines arranged on the substrate. The data lines and the scan lines define plural pixel regions....
US-9,559,124 Display panel
A display panel includes a first base substrate that includes an upper surface to which an external light is incident and a lower surface facing the upper...
US-9,559,122 Thin film transistor substrate and display
The invention provides a thin film transistor substrate includes: a substrate; and a plurality of transistors, wherein each of the transistors includes a gate...
US-9,559,120 Porous silicon relaxation medium for dislocation free CMOS devices
A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer...
US-9,559,119 High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on...
An electrical device including a first semiconductor device in a first region of the SOI substrate and a second semiconductor device is present in a second...
US-9,559,118 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
US-9,559,117 Three-dimensional non-volatile memory device having a silicide source line and method of making thereof
A memory device and a method of making a memory device that includes a stack of alternating layers of a first material and a second material different from the...
US-9,559,116 Semiconductor device
A semiconductor device may include an insulating layer provided in one body on a substrate, a first gate electrode and a second gate electrode disposed on the...
US-9,559,115 Three-dimensional semiconductor memory devices including a vertical channel
Semiconductor memory devices and methods of forming the semiconductor devices may be provided. The semiconductor memory devices may include a channel portion of...
US-9,559,114 Manufacturing method of three-dimensional non-volatile memory device including a selection gate having an L shape
A 3-dimensional (3-D) non-volatile memory device includes a first channel protruding from a substrate, a selection gate formed on sidewalls of the first channel...
US-9,559,113 SSL/GSL gate oxide in 3D vertical channel NAND
A memory device includes an array of strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material,...
US-9,559,112 Semiconductor devices and methods of fabricating the same
A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and...
US-9,559,111 Three-dimensional semiconductor memory device
A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate;...
US-9,559,110 Dense arrays and charge storage devices
There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface...
US-9,559,109 Memory including blocking dielectric in etch stop tier
Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to...
US-9,559,108 Chip and an electronic device
A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two...
US-9,559,107 Structure and method for BEOL nanoscale damascene sidewall-defined non-volatile memory element
An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to...
US-9,559,106 Memory cell that prevents charge loss
A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel...
US-9,559,105 Signal processing circuit
A signal processing circuit includes a memory and a control portion configured to control the memory. The control portion includes a volatile memory circuit...
US-9,559,104 Mask read-only memory array, memory device, and fabrication method thereof
A mask read-only memory array is provided. The mask read-only memory array includes a semiconductor substrate having a surface; and a heavily doped layer formed...
US-9,559,103 Memory device including selectively disposed landing pads expanded over signal line
Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured...
US-9,559,102 Semiconductor device
A semiconductor device includes first and second active regions. Each active region includes a plurality of fin protrusions and a recessed area disposed between...
US-9,559,101 Semiconductor device with impurity-doped region and method of fabricating the same
A semiconductor device includes an interlayer insulating film formed on a substrate, a plurality of contacts formed in the interlayer insulating film, and an...
US-9,559,100 Semiconductor device and manufacturing method thereof
A semiconductor device includes first and second Fin FET transistors and a separation plug made of an insulating material and disposed between the first and...
US-9,559,099 Apparatus and method for FinFETs
A FinFET device comprises an isolation region in a substrate, wherein the isolation region comprises a plurality of non-vertical sidewalls, a first V-shaped...
US-9,559,098 Semiconductor device including voltage dividing diode
In a semiconductor device connected to a mutual-inductive load, a voltage dividing diode is provided in series to an ST-MOS circuit so that an anode thereof is...
US-9,559,097 Semiconductor device with non-isolated power transistor with integrated diode protection
A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and...
US-9,559,096 Devices and methodologies related to structures having HBT and FET
A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including...
US-9,559,095 Semiconductor device
A semiconductor device is provided. The semiconductor device includes a first transistor on a first side of a shallow trench isolation (STI) region and a second...
US-9,559,094 Semiconductor device and integrated circuit
A semiconductor device includes a first semiconductor region that has an external profile including at least one corner, and that includes a semiconductor of a...
US-9,559,093 Method of forming a semiconductor device having a GaNFET, an overvoltage clamping component, and a voltage...
A method of forming a semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and...
US-9,559,092 Electronic device including a diode
An electronic device can include a substrate, lower and upper semiconductor layers over the substrate, and a doped region at the interface between the lower and...
US-9,559,091 Method of manufacturing fin diode structure
A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of...
US-9,559,090 Silicon wafer with a plurality of chip patterns
A silicon wafer includes a plurality of chip patterns arranged parallel to a first direction and a second direction intersecting the first direction, wherein...
US-9,559,089 Semiconductor arrangement with active drift zone
A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second...
US-9,559,088 Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first...
US-9,559,087 Techniques for packaging multiple device components
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a...
US-9,559,086 Semiconductor device with modified current distribution
Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a...
US-9,559,085 Method for producing an optoelectronic device and optoelectronic device
A method for producing an optoelectronic device is specified. A housing base body is formed with a self-healing polymer material. A recess is found in the...
US-9,559,084 Light-emitting device with multi-color temperature and multi-loop configuration
A light-emitting device with multi-color temperature and multi-loop configuration is provided. The light-emitting device may include a substrate, multiple light...
US-9,559,083 Semiconductor light-emitting device
Provided is a compact and high-luminance semiconductor light-emitting device which has excellent color rendering characteristics and which enables arbitrary...
US-9,559,082 Three-dimensional vertical memory comprising dice with different interconnect levels
The present invention discloses a three-dimensional vertical memory (3D-M.sub.V). It comprises at least a 3D-array die and at least a peripheral-circuit die....
US-9,559,081 Independent 3D stacking
Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a...
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