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Patent # Description
US-9,559,028 Semiconductor device
A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate...
US-9,559,027 Semiconductor device and semiconductor module
A semiconductor device includes a housing with a fragile portion. The fragile unit or portion has a resistance to a pressure or a melting point temperature that...
US-9,559,026 Semiconductor package having a multi-layered base
A semiconductor package for mounting to a printed circuit board (PCB) includes a semiconductor die in a ceramic case, a conductive base coupled to the...
US-9,559,025 Scan testable through silicon VIAs
The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of...
US-9,559,024 Power semiconductor module
A power semiconductor module, including a housing and a substrate having at least one conductive path is located, at least one power semiconductor device...
US-9,559,023 Systems and methods for reducing beam instability in laser annealing
Systems and methods for reducing beam instability in laser annealing are disclosed. The method includes: directing a conditioned laser beam through an opening...
US-9,559,022 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device, includes: forming a film, wherein the act of forming a film includes: transferring a substrate to a process...
US-9,559,021 Wafer back-side polishing system and method for integrated circuit device manufacturing processes
A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the...
US-9,559,020 Method for postdoping a semiconductor wafer
A method for treating a semiconductor wafer having a basic doping is disclosed. The method includes determining a doping concentration of the basic doping, and...
US-9,559,019 Metrology through use of feed forward feed sideways and measurement cell re-use
Metrology may be implemented during semiconductor device fabrication by a) modeling a first measurement on a first test cell formed in a layer of a partially...
US-9,559,018 Dual channel finFET with relaxed pFET region
Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of...
US-9,559,017 Method of forming shallow trench isolations for a semiconductor device
A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at...
US-9,559,016 Semiconductor device having a gate stack with tunable work function
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first...
US-9,559,015 Method of forming a conductive line pattern in FinFET semiconductor devices
The present invention provides a formation method of forming, on a substrate, a fin pattern in which a plurality of linear fins are arrayed, the method...
US-9,559,014 Self-aligned punch through stopper liner for bulk FinFET
A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins...
US-9,559,013 Stacked nanowire semiconductor device
A semiconductor device a first epitaxially grown source/drain region comprising a first material arranged on a first fin, a second epitaxially grown...
US-9,559,012 Gallium nitride complementary transistors
A semiconductor device includes a substrate, a III-nitride buffer layer on the substrate, an N-channel transistor including a III-nitride N-channel layer on one...
US-9,559,011 Mechanisms for forming FinFETs with different fin heights
Methods for forming a semiconductor device are provided. The method includes forming a first fin and a second fin over a substrate and forming a first isolation...
US-9,559,010 Asymmetric high-k dielectric for reducing gate induced drain leakage
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes...
US-9,559,009 Gate structure cut after formation of epitaxial active regions
A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of...
US-9,559,008 FinFET-based ESD devices and methods for forming the same
A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of...
US-9,559,007 Plasma etch singulated semiconductor packages and related methods
A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially...
US-9,559,006 Light emitting device and method of manufacturing light emitting device
A light emitting device includes a semiconductor light emitting element including a semiconductor stacked-layer body and an electrode disposed on a first...
US-9,559,005 Methods of packaging and dicing semiconductor devices and structures thereof
Methods of packaging and dicing semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging and dicing...
US-9,559,004 Semiconductor device and method of singulating thin semiconductor wafer on carrier along modified region within...
A semiconductor device comprises a carrier including an adhesive disposed over the carrier. The semiconductor device further comprises a semiconductor wafer...
US-9,559,003 Three-dimensional semiconductor architecture
A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate...
US-9,559,002 Methods of fabricating semiconductor devices with blocking layer patterns
A semiconductor device includes a circuit device on a substrate and a first insulating interlayer on the substrate and covering the circuit device. An electrode...
US-9,559,001 Chip package and method for forming the same
According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole...
US-9,559,000 Hybrid logic and SRAM contacts
The method includes forming a first opening in a dielectric layer exposing a source drain region of an SRAM device and forming a second opening in the...
US-9,558,999 Ultra-thin metal wires formed through selective deposition
The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for...
US-9,558,998 Systems and methods for producing flat surfaces in interconnect structures
In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect...
US-9,558,997 Integration of Ru wet etch and CMP for beol interconnects with Ru layer
Embodiments described herein provide approaches for interconnect formation in a semiconductor device. Specifically, a Cu layer is removed to a top surface of an...
US-9,558,996 Method for filling trench with metal layer and semiconductor structure formed by using the same
A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a...
US-9,558,995 HDP fill with reduced void formation and spacer damage
A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first...
US-9,558,994 Semiconductor devices and methods of fabricating the same
A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced...
US-9,558,993 Pattern structures in semiconductor devices and methods of forming pattern structures in semiconductor devices
A pattern structure in a semiconductor device includes an extending line and a pad connected with an end portion of the extending line. The pad may have a width...
US-9,558,992 Metal wiring of semiconductor device and method for manufacturing the same
A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region...
US-9,558,991 Formation of isolation surrounding well implantation
Embodiments of present invention provide a method of making well isolations. The method includes forming a hard-mask layer on top of said substrate; forming a...
US-9,558,990 Semiconductor device and method for forming the same
A semiconductor device and a method for forming the same can block a moving path of electrons between neighbor buried gates. A semiconductor device includes a...
US-9,558,989 Method for manufacturing semiconductor device
After embedding a silicon oxide film within a second trench that opens in a semiconductor substrate using a silicon nitride film as a hard mask, the silicon...
US-9,558,988 Method for filling the trenches of shallow trench isolation (STI) regions
A method for manufacturing a shallow trench isolation (STI) region with a high aspect ratio is provided. A semiconductor substrate is provided with a trench. A...
US-9,558,987 Gap-fill methods
Gap-fill methods comprise: (a) providing a semiconductor substrate having a relief image on a surface of the substrate, the relief image comprising a plurality...
US-9,558,986 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the...
US-9,558,985 Vacuum chuck
A vacuum chuck is disclosed for holding and positioning wafers more stably and securely. The vacuum chuck includes a supporting assembly having a receiving...
US-9,558,984 Device for holding a planar substrate
A device (1) for holding a planar substrate (4), in particular for a wafer or an eWLB, is shown, with a support (2) which forms a supporting surface (3) for the...
US-9,558,983 Base film for dicing sheet and dicing sheet
A base film for a dicing sheet is provided which can suppress dicing debris from generating during the dicing of a cut object without imparting physical energy,...
US-9,558,982 Minimal contact edge ring for rapid thermal processing
Embodiments of the disclosure generally relate to a support ring that supports a substrate in a process chamber. In one embodiment, the support ring comprises...
US-9,558,981 Control systems employing deflection sensors to control clamping forces applied by electrostatic chucks, and...
A control system that includes deflection sensors which can control clamping forces applied by electrostatic chucks, and related methods are disclosed. By using...
US-9,558,980 Vapor compression refrigeration chuck for ion implanters
Aspects of the present invention relate to ion implantation systems that make use of a vapor compression cooling system. In one embodiment, a thermal controller...
US-9,558,979 Method for manufacturing semiconductor device
A wafer chuck holds a wafer on a surface thereof such that an image of the wafer can be formed from light reflected by the surface of the wafer chuck. The...
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